Tilted Gate Spacer Structure to Prevent GAA FET Short Circuits
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Solution Overview
Problem
Existing methods for forming non-planar transistor devices, such as GAA FETs, face issues with short circuits between the active gate structure and source/drain structures due to the remnants of the etch stop layer, leading to improper functioning of transistors.
Innovation Solution
The etch stop layer is patterned before forming the gate spacer, creating a mesa-like profile that isolates the etch stop layer, preventing short circuits and allowing for a wider process window in forming the active gate structure, which wraps around the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etch stop layer is not patterned before forming the gate spacer, then the manufacturing process is simpler, but short circuits occur between the active gate structure and source/drain structures
Solution Approach 1:
The etch stop layer is patterned in advance before forming the gate spacer, creating a mesa-like profile that isolates the etch stop layer. This preliminary action prevents short circuits between the active gate structure and source/drain structures by establishing isolation features before subsequent structures are formed.
Solution Approach 2:
The etch stop layer is segmented into isolated regions through patterning, creating distinct mesa-like profiles. This segmentation isolates different functional areas and prevents electrical short circuits between adjacent structures while maintaining the necessary electrical connections within each region.
2Adaptability or versatility
If the etch stop layer is patterned to create a mesa-like profile, then the process window for forming the active gate structure is wider, but the manufacturing precision requirements increase
Solution Approach 1:
The etch stop layer is patterned in advance to create a mesa-like profile with isolated regions. This preliminary structuring establishes a robust foundation that accommodates variations in subsequent processing steps, thereby widening the process window for forming the active gate structure while maintaining adequate precision through the self-aligned nature of the approach.
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.