Tilted Hemi-Cylindrical 3D NAND Array for Gate Controllability
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Solution Overview
Problem
Current memory devices face limitations in gate controllability and storage capacity due to the narrow channel width and interference between memory cells in single gate and flat channel structures, which restricts storage density and efficiency.
Innovation Solution
The implementation of a three-dimensional memory device with tilted hemi-cylindrical vertical channel structures and tri-gate or finFET-like double-gate configurations, where the channel material extends around a cylindrical structure with a divided elliptical cross-section, enhancing channel width and reducing interference by altering the gate width and orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate and flat channel structure is used, then the device structure is simple, but the gate controllability is limited and the channel width is narrow
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a three-dimensional vertical channel structure. The channel extends vertically through multiple conductive layers, creating a 3D architecture that increases gate controllability while maintaining manufacturing feasibility. This dimensional change allows the gate to control current flow more effectively in the vertical direction.
Solution Approach 2:
The patent employs curved or cylindrical channel structures instead of flat planar channels. The vertical channel extends upward from the substrate with a curved profile, and the gate wraps around portions of this curved channel, creating a cylindrical or arc-shaped gate-channel interface that enhances control effectiveness.
2Ease of manufacture
If a single gate and flat channel structure is used, then the manufacturing process is simple, but the channel width is narrow limiting storage capacity
Solution Approach 1:
The patent stacks multiple conductive layers vertically to create a three-dimensional memory array, increasing the number of storage cells per unit area. This vertical stacking approach multiplies storage capacity without requiring proportional increases in lateral manufacturing complexity, as each layer can be formed using similar fabrication processes.
Solution Approach 2:
The patent implements a nested structure where vertical channels are embedded within stacked conductive layers. The channels extend through multiple alternating layers of conductive and insulating materials, creating a nested configuration where storage elements are embedded within the layered structure, maximizing space utilization.
3Area of stationary object
If opposite cells are arranged on sidewalls of a flat structure, then the layout is compact, but Y-interference occurs between opposite cells
Solution Approach 1:
The patent arranges memory cells in a three-dimensional configuration with vertical separation between opposing cells. Instead of placing cells directly opposite each other in the same planar layer, the structure uses multiple stacked layers where opposing cells are separated by insulating layers, reducing capacitive coupling and interference while maintaining compact footprint.
Solution Approach 2:
The patent introduces insulating layers as intermediary barriers between opposing conductive channels on opposite sidewalls. These insulating layers physically separate and electrically isolate adjacent channels, preventing Y-interference while allowing the compact vertical stacking architecture to be maintained.
Data Source
AI summary
A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.