Tilted Heterostructures for UV LED Carrier Injection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing UV LEDs face challenges in achieving high carrier concentration in the light generating structure due to the high ionization energy of acceptor impurities in group III nitride materials, leading to inefficient p-type doping and increased turn-on voltage.
Innovation Solution
The formation of tilted semiconductor heterostructures with two-dimensional carrier accumulation (2DCA) layers at heterointerfaces between materials with different compositions, which enhance hole/electron injection efficiency by creating two-dimensional gas (2DG) layers, allowing for efficient carrier injection into the light generating structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high p-type doping is used in group III nitride materials, then carrier concentration in the light generating structure is improved, but turn-on voltage increases due to high ionization energy of acceptor impurities
Solution Approach 1:
The patent introduces an electron blocking layer as an intermediary component between the n-type semiconductor layer and the light generating structure. This layer has higher electron affinity than the adjacent layers, creating a potential barrier that blocks electrons from entering the light generating structure while allowing holes to pass through. This mediator approach enables efficient carrier injection without requiring excessive doping concentrations that would increase turn-on voltage.
Solution Approach 2:
The patent applies local quality by creating a heterostructure with spatially varying composition and properties. The electron blocking layer is positioned specifically at the interface where electron management is critical, while other regions maintain their original doping and composition characteristics. This localized modification allows optimal electron blocking function without compromising overall device performance or requiring global changes that would increase voltage.
2Quantity of substance
If additional interfaces or barriers are added to enhance carrier injection, then carrier concentration in the light generating structure is improved, but device complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into functionally distinct layers with specific roles: an n-type semiconductor layer for electron supply, an electron blocking layer for electron management, and a light generating structure for photon emission. This segmentation allows each layer to be optimized independently for its specific function, achieving high carrier concentration in the light generating structure through clear functional division rather than complex interwoven structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier injection efficiency by forming 2DG layers at heterointerfaces, reducing resistance and increasing the concentration of carriers in the light generating structure, thereby enhancing the performance of UV LEDs.
Implementation Method 1
tilted semiconductor heterostructures having two-dimensional carrier accumulation (2DCA) layers for improved carrier injection
Implementation Method 2
forming two-dimensional gas (2DG) layers at a hetero-interface between two materials with different compositions in order to enhance hole/electron injection efficiency
Data Source
AI summary
An opto-electronic device with two-dimensional injection layers is described. The device can include a semiconductor structure with a semiconductor layer having one of an n-type semiconductor layer or a p-type semiconductor layer, and a light generating structure formed on the semiconductor layer. A set of tilted semiconductor heterostructures is formed over the semiconductor structure. Each tilted semiconductor heterostructure includes a core region, a set of shell regions adjoining a sidewall of the core region, and a pair of two-dimensional carrier accumulation (2DCA) layers. Each 2DCA layer is formed at a heterointerface between one of the sidewalls of the core region and one of the shell regions. The sidewalls of the core region, the shell regions, and the 2DCA layers each having a sloping surface, wherein each 2DCA layer forms an angle with a surface of the semiconductor structure.