Tilted Die-Encapsulation Interface for High-Density Fan-Out Packaging
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in efficiently integrating a high number of I/O pads due to limited pitch and solder bridge issues, especially as semiconductor dies become smaller, affecting yield and packaging complexity.
Innovation Solution
A fan-out packaging method is employed, involving a tilted interface between the device die and encapsulating material, with grooved trenches and tilted sidewalls to facilitate redistribution of I/O pads, reducing stress and deformation during encapsulation, and allowing for increased I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging with limited pitch is used, then manufacturing process is simpler, but the number of I/O pads is limited and solder bridges may occur
Solution Approach 1:
The patent transitions from planar 2D pad arrangement to 3D vertical stacking by introducing multiple stacked dies with through-silicon vias (TSVs). This dimensional change allows I/O pads to be distributed across multiple layers, effectively increasing the total number of I/O pads without increasing the footprint area, thereby resolving the contradiction between pad quantity and packaging complexity.
Solution Approach 2:
The patent implements a nested structure where multiple dies are stacked vertically with each die containing I/O pads, and the entire stack is enclosed within a package substrate. This nesting approach allows compact integration of multiple functional units, increasing I/O density while maintaining manageable packaging complexity through hierarchical organization.
2Quantity of substance
If I/O pad pitch is decreased to increase pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
By moving from 2D planar arrangement to 3D vertical stacking with TSVs, the patent achieves high I/O pad density without decreasing the pitch within each individual pad layer. The vertical dimension provides additional space for I/O connections, maintaining adequate pad spacing while increasing overall pad capacity, thus avoiding solder bridge issues.
Solution Approach 2:
The patent introduces TSVs as intermediary structures that provide electrical connections between stacked dies. These TSVs act as mediators that distribute I/O signals vertically, allowing high-density I/O integration without requiring reduced horizontal pitch, thereby maintaining solder joint reliability while achieving high I/O pad density.
3Productivity
If fan-in packaging is used for smaller dies, then throughput is higher and cost is lower, but the number of I/O pads is limited by die area
Solution Approach 1:
The patent combines fan-in packaging benefits with 3D vertical stacking using TSVs. This allows high-volume manufacturing through standardized die stacking processes while achieving high I/O pad capacity by utilizing the vertical dimension. Multiple dies can be stacked to increase I/O capacity without requiring larger die areas, maintaining the throughput and cost advantages of fan-in packaging.
Solution Approach 2:
The patent merges the advantages of fan-in packaging (high throughput, low cost) with the capabilities of fan-out packaging (high I/O density) by implementing a hybrid approach. Multiple small dies are stacked and interconnected using TSVs, creating a compact high-density package that maintains manufacturing efficiency while achieving high I/O pad capacity.
Data Source
AI summary
A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.