Tilted Ion Implantation for Integrated Power MOSFET Grooves

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Solution Overview

Problem

The challenge lies in simplifying the manufacturing process of semiconductor devices that integrate both n-channel and p-channel power MOSFETs on a single semiconductor substrate while maintaining low on-state resistance and high voltage blocking capability, which is crucial for automotive and industrial electronics.

Innovation Solution

The method involves forming first and second field effect transistors on a semiconductor substrate with tilted ion implantation processes to create source and drain contact grooves in different directions, allowing for the introduction of dopants of specific conductivity types, thereby simplifying the manufacturing process and enhancing the integration of transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If n-channel and p-channel power MOSFETs are integrated into one single semiconductor substrate, then device functionality and versatility are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveintegration of n-channel and p-channel power MOSFETsVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of source and drain contact grooves for both n-channel and p-channel MOSFETs into a single etching step, creating grooves in different directions simultaneously. This merging of steps simplifies the manufacturing process while achieving full integration of complementary transistor types on one substrate.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces tilted ion implantation at angles of 45 degrees relative to the substrate surface, adding a dimensional aspect to the doping process. This allows dopants to be introduced through the sidewalls of contact grooves rather than only through the bottom, enabling selective doping of different transistor regions through a single implantation step.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If tilted ion implantation processes are used to introduce dopants through sidewalls, then manufacturing precision and doping control are improved, but process complexity increases

Engineering Contradiction:
Improvedoping control precisionVSAvoidion implantation process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the implantation angle parameter from the conventional perpendicular (0 degrees) to tilted (45 degrees), which fundamentally alters the doping profile and enables sidewall doping. This parameter change allows precise control over dopant distribution in three-dimensional space, achieving high manufacturing precision while the complexity is managed through process integration.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The tilted ion implantation process serves multiple functions simultaneously: it dopes the sidewalls of contact grooves, creates appropriate doping profiles for both n-channel and p-channel MOSFETs, and enables selective doping through geometric relationships with the contact groove orientation. This multi-functionality reduces the need for separate doping steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If source contact grooves and drain contact grooves are formed in different directions, then transistor integration and electrical characteristics are improved, but manufacturing steps increase

Engineering Contradiction:
Improvetransistor integration capabilityVSAvoidmanufacturing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the formation of source and drain contact grooves for both n-channel and p-channel MOSFETs into a single etching step, creating grooves in different directions simultaneously. This merging of steps simplifies the manufacturing process while achieving full integration of complementary transistor types on one substrate.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs and improves the integration of transistors, enabling better electrical characteristics and higher breakdown voltages, which is essential for high-performance automotive and industrial electronics.

Implementation Method 1

performing a first tilted ion implantation process with dopants of the first conductivity type, the first tilted ion implantation process being performed in a first implantation direction, a projection of the first implantation direction on the first main surface being perpendicular to the first direction, the first implantation direction having a first tilt angle with respect to a normal to the first main surface, so as to introduce dopants through first sidewalls of the first source contact groove and the first drain contact groove into the semiconductor substrate

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9661707B2Method for manufacturing a semiconductor device using tilted ion implantation processes, semiconductor device and integrated circuit
Publication Date: 2017.05.23 INFINEON TECHNOLOGIES AG
  • US9661707B2 patent drawing
  • US9661707B2 patent drawing
  • US9661707B2 patent drawing

AI summary

A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.