Tilted Source Drain Extension Regions for Leakage Reduction
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Solution Overview
Problem
Conventional MOS transistors face challenges with high gate-induced drain leakage (GIDL) current and hot carrier effects due to heavily doped source and drain extension regions, which also lead to increased sheet resistance and gate-drain overlap capacitance, affecting device reliability and performance.
Innovation Solution
The semiconductor device features tilted and bended source drain extension (SDE) regions with lightly doped profiles, allowing for reduced GIDL current and gate-drain overlap capacitance without decreasing the concentration of doped regions, and thinner spacers that enable a stress layer closer to the channel region, enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavily doped source and drain extension regions are used, then device performance is improved, but gate-induced drain leakage current and hot carrier effect increase
Solution Approach 1:
The patent applies local quality by creating a graded doping profile in the source and drain extension regions, where the doping concentration varies spatially - lighter near the gate to reduce GIDL and hot carrier effects, and heavier toward the source/drain regions to maintain device performance. This non-uniform doping distribution optimizes both reliability and performance simultaneously.
2Object-generated harmful factors
If dosage of source and drain extension regions is decreased, then gate-induced drain leakage and hot carrier effect are reduced, but sheet resistance and gate-drain overlap capacitance increase
Solution Approach 1:
The patent changes the doping concentration parameter by implementing a graded doping profile that transitions from lighter doping near the gate to heavier doping toward the source/drain regions. This parameter variation allows the SDE regions to maintain low GIDL and hot carrier effects while preserving adequate sheet resistance and capacitance characteristics.
Data Source
AI summary
A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.