Tilted Through Silicon Via Chip Package Design
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Solution Overview
Problem
Conventional chip stacking technologies face challenges with signal delays and increased package size due to long wires, which are necessary for chip selection in memory chip stacks, and risk signal trace shortages in fine-pitch products.
Innovation Solution
A chip package design featuring a substrate with tilted through silicon vias and chip selection wiring, which reduces the signal transmitting path by using tilted connection wirings to connect chip selection terminals and other connection terminals, thereby minimizing wire length and optimizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wires are used to connect chip selection terminals in memory chip stacks, then chip selection functionality is achieved, but signal transmission path length increases causing signal delays and larger package size
Solution Approach 1:
The patent introduces tilted through-silicon vias (TSVs) that extend diagonally through the substrate rather than vertically or horizontally. This three-dimensional routing approach allows signal paths to cut through the substrate at an angle, effectively reducing the transmission distance compared to conventional wire routing while maintaining electrical connectivity between chip selection terminals and external contacts.
Solution Approach 2:
The tilted TSV structure creates a diagonal signal path through the substrate that optimizes the routing geometry. By angling the vias, the patent achieves a more direct signal transmission path that reduces length while accommodating the three-dimensional stacked chip architecture.
2Reliability
If conventional wires are used for chip selection in memory chip stacks, then chip selection is enabled, but package size increases due to longer wire paths
Solution Approach 1:
By transitioning from planar wire routing to three-dimensional tilted via routing, the patent reduces the horizontal space required for signal paths. The diagonal orientation of TSVs allows chip selection signals to reach their destinations more directly, reducing the overall footprint and package volume while maintaining full chip selection functionality across stacked memory chips.
3Volume of stationary object
If fine-pitch products are used to reduce package size, then package dimensions are reduced, but signal trace shortages occur due to insufficient space for conventional wiring
Solution Approach 1:
The tilted TSV architecture fundamentally changes the routing paradigm from two-dimensional wire traces on the surface to three-dimensional vertical and diagonal pathways through the substrate. This enables fine-pitch products to achieve compact dimensions while maintaining adequate signal trace space, as the tilted vias utilize the substrate thickness dimension rather than consuming horizontal routing space.
Solution Approach 2:
The patent divides the signal transmission path into multiple segments: the tilted via portion through the substrate, the vertical interconnect portion, and the horizontal routing portion. This segmentation allows each segment to be optimized independently, enabling compact overall design while ensuring sufficient space for signal traces in fine-pitch implementations.
4Speed
If tilted through silicon via is used to reduce wire length, then signal transmission efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates tilted TSV formation as an early step in the manufacturing process, before final chip stacking and packaging. By pre-forming the tilted vias in the substrate during initial fabrication, the complex tilted structure is created once rather than requiring complex post-assembly alignment and routing operations, thereby reducing overall manufacturing complexity despite the non-standard via geometry.
Data Source
AI summary
A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion.