Time Aligning Circuit for Multi-Lane Data Skew Compensation
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Solution Overview
Problem
The existing PCI-Express bus systems face timing alignment issues due to differences in lane lengths, impedance, and operating clock frequencies, leading to data transmission skew and inconsistencies, which result in data overflow or underflow problems.
Innovation Solution
A time aligning circuit comprising buffers, delay selectors, adjustment symbol generators, and a control unit that detects initial symbols and generates delay and adjustment control signals to synchronize data transmission across multiple lanes, addressing timing offsets caused by various factors including lane differences and elastic buffer adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple lanes are used to transmit data simultaneously, then data transfer performance is improved, but timing alignment between lanes deteriorates due to different lane lengths and impedance
Solution Approach 1:
The patent applies preliminary action by inserting delay elements before the data transmission begins. The delay element generates delay signals that are fed back to control the transmission timing of each lane, ensuring that data from different lanes arrives simultaneously at the receiving end before actual data transfer occurs.
Solution Approach 2:
The patent implements feedback by using delay elements to generate delay signals that are fed back to control the transmission timing. The feedback mechanism continuously monitors the timing alignment and adjusts the delay signals to maintain synchronization across all lanes during data transmission.
2Reliability
If elastic buffers are used to regulate data transmission, then data overflow and underflow are prevented, but timing alignment between lanes deteriorates due to inconsistent SKP symbol counts
Solution Approach 1:
The patent uses feedback mechanisms to monitor the timing alignment and adjust the delay signals accordingly. When elastic buffers introduce variations in SKP symbol counts, the feedback system detects the timing discrepancies and generates appropriate delay signals to compensate, ensuring consistent timing across all lanes while maintaining data reliability.
3Speed
If different operating clock frequencies are used for transmitting and receiving devices, then data transmission rate can be adjusted, but timing alignment and data consistency deteriorate
Solution Approach 1:
The patent applies preliminary action by generating delay signals before data transmission begins, based on the difference between transmitting and receiving clock frequencies. These delay signals are pre-calculated to compensate for the frequency difference, ensuring that data from multiple lanes arrives simultaneously even when operating at different clock frequencies.
Solution Approach 2:
The patent implements feedback by continuously monitoring timing alignment and adjusting delay signals in response to clock frequency differences. The feedback mechanism ensures that despite different operating frequencies, the data transmission timing remains synchronized across all lanes, maintaining data consistency while allowing flexible speed adjustment.
Data Source
AI summary
A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.