Time-Aware DMA Controller for Deterministic Memory Access
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Solution Overview
Problem
Traditional DMA systems fail to guarantee time precision required by time-sensitive applications, leading to inter-stream interference and limited scalability in supporting multiple time-sensitive applications.
Innovation Solution
A multi-channel time-aware DMA (TADMA) method that includes a memory access control circuit with a timing control circuit to determine fetch times based on timing requirements, ensuring precise data transfers and reducing inter-stream interference by implementing a per-stream time-aware scheduling mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DMA system is used, then data transfer can be performed without device intervention, but time precision required by time-sensitive applications cannot be guaranteed
Solution Approach 1:
The DMA controller is segmented into multiple independent channels, each capable of handling time-sensitive streams autonomously. Each channel has dedicated timing control logic that operates independently, allowing multiple streams to be transferred with guaranteed time precision without requiring complex centralized scheduling.
Solution Approach 2:
The system dynamically adjusts fetch timing based on stream priority and timing requirements. The timing control circuit generates dynamic fetch start times that adapt to real-time conditions, allowing the system to maintain time precision guarantees while handling varying traffic patterns across different streams.
2Reliability
If traditional DMA system is used, then simple data transfer is achieved, but inter-stream interference occurs in time-sensitive applications
Solution Approach 1:
Multiple independent DMA channels are implemented, with each channel dedicated to specific streams. This segmentation isolates streams from each other, preventing inter-stream interference while maintaining simple transfer operations within each channel. High-priority and low-priority streams are separated into different channels.
Solution Approach 2:
Each DMA channel is configured with specific timing control characteristics appropriate for its assigned streams. The timing control circuit applies different timing parameters and fetch strategies locally to each channel based on the specific requirements of the streams it handles, rather than using a uniform approach for all streams.
3Adaptability or versatility
If traditional DMA system is used, then basic memory access is performed, but scalability for supporting multiple time-sensitive applications is limited
Solution Approach 1:
The DMA controller is divided into multiple independent channels, each capable of handling time-sensitive streams autonomously. This segmentation allows the system to scale to support multiple applications by simply activating additional channels rather than increasing the complexity of a centralized controller.
Solution Approach 2:
Timing parameters and stream configurations are pre-configured for each channel before operation begins. The timing control circuit uses these pre-configured parameters to automatically generate appropriate fetch timing without requiring complex real-time calculations, enabling scalable support for multiple applications with consistent time precision guarantees.
Data Source
AI summary
A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.