Time-Based Block Family Merging for Memory Voltage Shift
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Solution Overview
Problem
Existing memory sub-systems face increased bit error rates due to temporal voltage shift caused by slow charge loss in memory cells, which current technologies inadequately address, leading to inefficient strategies and high error rates.
Innovation Solution
Implementing a memory sub-system that tracks temporal voltage shift for block families and applies appropriate voltage offsets to base read levels, allowing for the combination of block families based on time and voltage criteria to manage error rates and reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If block families are tracked separately with individual voltage offsets, then read operation accuracy is improved, but device complexity and overhead increase
Solution Approach 1:
The patent combines multiple block families into a single block family when they share similar voltage distribution characteristics. Instead of maintaining separate voltage offset calibration data for each block family, the system merges them and uses a single shared calibration dataset, thereby reducing metadata overhead and device complexity while preserving read accuracy for blocks with similar voltage profiles
Solution Approach 2:
The patent creates a universal voltage offset calibration approach where a single calibration dataset serves multiple block families. By identifying blocks with similar voltage distributions and assigning them to the same block family, the system achieves multi-functionality where one calibration set benefits multiple blocks, reducing overall system complexity without sacrificing measurement precision
2Reliability
If voltage offsets are applied to compensate for temporal voltage shift, then bit error rate is reduced, but device complexity increases
Solution Approach 1:
The patent segments blocks into distinct block families based on their voltage distribution characteristics and time since programming. By grouping blocks with similar temporal voltage shift patterns, the system applies segmentation to create manageable groups that can be calibrated efficiently, reducing the overall complexity of managing voltage offsets across the entire memory device
Solution Approach 2:
The patent changes the parameter of voltage offset calibration from a per-block basis to a per-block-family basis. By adjusting the granularity of calibration from individual blocks to grouped block families, the system reduces the number of calibration parameters that need to be stored and managed, thereby reducing device complexity while maintaining error correction effectiveness through targeted voltage offset application
Data Source
AI summary
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.