Time-Based Decision Feedback Equalizer for High-Speed Serial Links
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Solution Overview
Problem
Current decision feedback equalizer (DFE) technologies for high-speed serial links face challenges such as high power consumption, reliance on complex analog circuits, and limited scalability, making them unsuitable for on-chip applications due to issues like inter-symbol interference (ISI) and parasitic capacitance, which affect data integrity and require significant redesign in new technologies.
Innovation Solution
The implementation of time-based decision feedback equalizer (TB-DFE) circuits using digital inverters and digitally-controlled delay elements, which perform weighted sum filter operations entirely in the time domain, converting input voltage signals into time-based signals and adjusting their timing based on weighted previous samples to compensate for ISI, thereby improving signal fidelity without static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decision feedback equalizer (DFE) circuits are used for high-speed serial links, then signal equalization can be achieved, but power consumption increases and design complexity increases
Solution Approach 1:
The patent replaces traditional analog DFE circuits with a time-based digital DFE circuit. The voltage-to-time converter transforms analog voltage signals into time-based signals, and digitally-controlled delay elements perform the equalization function that was previously achieved through analog mechanisms. This substitution of analog systems with digital/time-based systems reduces power consumption and design complexity while maintaining equalization effectiveness.
Solution Approach 2:
The patent changes the fundamental parameter domain from voltage-based analog signaling to time-based digital signaling. By converting the equalization operation from the voltage domain to the time domain, the system achieves the same signal restoration function with digital circuitry that consumes less power and has simpler design requirements compared to traditional analog DFE implementations.
2Productivity
If complex analog circuits are used in decision feedback equalizers, then signal processing capability is improved, but device complexity increases and scalability is limited
Solution Approach 1:
The patent substitutes complex analog signal processing circuits with time-based digital processing. The voltage-to-time converter and digitally-controlled delay elements implement equalization functions using digital logic and time-domain operations, replacing the need for complex analog components such as continuous-time filters and analog feedback networks. This reduces device complexity and improves scalability to advanced technology nodes.
Solution Approach 2:
The patent transitions the equalization operation from the voltage amplitude dimension to the time dimension. Instead of manipulating signal amplitude through complex analog circuits, the system uses time-based representation where signal information is encoded in timing relationships. This dimensional change enables simpler digital implementation while maintaining signal processing capability.
3Speed
If on-chip data buses with high resistance and capacitance are used, then data transmission within IC is enabled, but signal fidelity deteriorates due to inter-symbol interference
Solution Approach 1:
The patent applies preliminary equalization action through the time-based DFE circuit before the signal is fully processed. The voltage-to-time converter and delay elements pre-compensate for inter-symbol interference by adjusting timing relationships based on previous signal samples. This preliminary correction of signal degradation maintains fidelity even at high transmission rates over resistive and capacitive on-chip interconnects.
Solution Approach 2:
The patent implements feedback through the decision feedback equalizer structure, where previous output samples are fed back through the delay circuits and combined with the current input signal. This feedback mechanism continuously compensates for inter-symbol interference caused by the RC characteristics of on-chip data buses, maintaining signal fidelity at high transmission rates.
Data Source
AI summary
A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.