Time-Based ZQ Arbitration for Multi-Chip Impedance Calibration
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Solution Overview
Problem
Conventional arbitration schemes for semiconductor memory devices with multiple chips struggle to efficiently manage ZQ resistor access, leading to increased calibration time and power consumption, especially in low-power devices where voltage-based arbitration schemes fail to differentiate between multiple states effectively.
Innovation Solution
A time-based arbitration scheme with a unique ZQ timing pattern for each chip, using an arbiter circuit that includes a comparator and ZQ calibration circuit to manage access to a shared ZQ resistor, allowing multiple chips to calibrate simultaneously without extending calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage based arbitration scheme is used to determine ZQ calibration request priority, then arbitration can be implemented, but low-power devices cannot effectively differentiate between multiple states
Solution Approach 1:
The patent changes the arbitration parameter from voltage-based to time-based. Each chip is assigned a unique time delay value, and arbitration is performed by comparing the timing of ZQ calibration requests rather than voltage levels. This allows low-power devices to effectively participate in arbitration without requiring high voltage differentiation capability.
2Adaptability or versatility
If time based arbitration scheme with unique time delay for each chip is used, then any number of chips can use the ZQ resistor, but the required time increases exponentially according to the number of chips
Solution Approach 1:
The patent segments the time-based arbitration into multiple phases or groups. Instead of sequentially arbitrating all chips one by one which would take exponential time, the arbitration process is divided into segments that can be handled more efficiently, reducing the overall calibration time while still supporting multiple chips.
Solution Approach 2:
The patent implements preliminary action by pre-configuring time delay values for each chip before arbitration begins. This allows the arbitration process to proceed more efficiently by comparing pre-established timing references rather than establishing delays dynamically during arbitration, thereby reducing the total calibration time.
3Ease of operation
If conventional arbitration schemes are used for multiple chips, then ZQ resistor access can be managed, but calibration time increases
Solution Approach 1:
The patent replaces the conventional voltage-based mechanical/electrical arbitration system with a time-based arbitration mechanism. By substituting voltage comparison with time delay comparison, the system achieves faster arbitration that doesn't scale poorly with the number of chips, thereby reducing calibration time while maintaining ease of access management.
Data Source
AI summary
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.