Time-Borrowing Voltage Scaling With Local Boosting for Pipeline Delay Faults

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Solution Overview

Problem

Current dynamic voltage scaling systems face inefficiencies in power consumption reduction and data throughput, as they require additional cycles for error recovery and are limited by process variations, leading to unsatisfactory performance.

Innovation Solution

A dynamic voltage scaling system with time borrowing and local boosting capabilities, utilizing a time borrowing circuit and local boost circuit to delay data fetching and raise the working voltage of the next stage pipeline, thereby offsetting delay faults without reducing data throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If dynamic voltage scaling is used to reduce power consumption, then power consumption is reduced, but system performance and data throughput are degraded due to additional error recovery cycles

Engineering Contradiction:
Improvepower consumptionVSAvoiddata throughput
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing error detection and time borrowing setup before the actual computation stage. The critical path monitor continuously monitors signal propagation delays in advance, and when a delay fault is detected, the time borrowing mechanism is pre-configured by capturing the erroneous data state and preparing the compensation path, allowing the main computation to proceed without interruption and maintaining high data throughput while still correcting errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary mechanism in the form of a time borrowing buffer and compensation path that mediates between the primary computation path and the error correction requirement. When a delay fault occurs, the intermediary buffer captures the intermediate data state and provides a compensated output path that bypasses the faulty stage, allowing error correction without stalling the pipeline and thus maintaining data throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If design margin is reserved in CPM to ensure logic circuit operation under process variations, then reliability is improved, but voltage scaling capability is reduced

Engineering Contradiction:
Improvelogic circuit operation reliabilityVSAvoidvoltage scaling capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the CPM's monitoring threshold and the voltage scaling level dynamic rather than static. The critical path monitor continuously adapts its reference delay value based on actual process variations and operating conditions, allowing the system to maintain reliable operation across process variations while maximizing voltage scaling. The voltage level is dynamically adjusted based on real-time delay measurements, enabling the system to operate at the highest possible voltage without errors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of the CPM's delay threshold from a fixed design margin to a variable parameter that adapts to process variations. By continuously measuring the actual critical path delay and adjusting the monitoring threshold accordingly, the system reduces the excessive design margin required for worst-case scenarios, thereby enabling more aggressive voltage scaling while maintaining reliability under actual operating conditions.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If voltage is reduced to save power, then power consumption is reduced, but delay faults increase due to process variations

Engineering Contradiction:
Improvepower consumptionVSAvoiddelay fault rate
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent implements feedback by using the critical path monitor to continuously measure signal propagation delays and feed this information back to the voltage controller. When the monitor detects that the actual delay approaches the critical threshold, it triggers a voltage adjustment to prevent delay faults. This closed-loop feedback mechanism allows the system to operate at higher voltages than static analysis would suggest, reducing delay faults while maintaining power efficiency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary detection of potential delay faults through continuous monitoring of the critical path. By detecting delay accumulation before it causes actual computation errors, the system can proactively adjust voltage levels or activate time borrowing mechanisms, preventing delay faults from occurring in the first place and maintaining reliability at reduced voltage levels.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8933726B2Dynamic voltage scaling system having time borrowing and local boosting capability
Publication Date: 2015.01.13 NATIONAL CHUNG CHENG UNIV
  • US8933726B2 patent drawing
  • US8933726B2 patent drawing
  • US8933726B2 patent drawing

AI summary

A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line.