System Time Bus Error Detection for Processor Synchronization
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Solution Overview
Problem
In automotive processing systems, ensuring precise synchronization of operations across multiple processing units is challenging due to the complexity of modern systems and the need for reliable time references, which is critical for safety and security but often compromised by malfunctions in time-base value generation and distribution.
Innovation Solution
A processing system with a timer circuit generating a system time signal, transmitted via a parallel time bus, and error detection circuits to ensure accuracy and integrity of the time reference, including error correction and watchdog timers to monitor correct evolution of the system time, thereby ensuring reliable operation and safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a timer circuit generates and distributes system time signals to multiple processing units, then synchronization across processing units is improved, but the complexity of the system increases due to additional error detection circuits and parallel time bus infrastructure
Solution Approach 1:
The patent introduces a parallel time bus as an intermediary component that专门负责传输时间基准信号。这个中间介质将计时电路与多个处理单元连接起来，使得时间同步功能独立于其他系统功能，从而在提高同步可靠性的同时，通过模块化设计控制了系统整体的复杂性
Solution Approach 2:
在时间信号传输到处理单元之前，专利在计时电路端预先设置了错误检测电路，对时间基准值的生成过程进行实时监控和错误检测。这种预先行动确保了只有经过验证的正确时间信号才被传输，从而在提高同步可靠性的同时避免了事后复杂的错误处理和系统重置
2Measurement precision
If error detection circuits are added to monitor system time signals, then the correctness and integrity of time reference is improved, but the device complexity and power consumption increase
Solution Approach 1:
错误检测电路被设计为自服务系统，能够自动检测、识别和报告时间基准值的错误，无需外部干预。通过自我诊断功能，系统在发现错误时可以自动触发复位或切换备用时间源，这种自服务能力提高了时间参考的准确性，同时避免了复杂的人工监控和处理机制
Solution Approach 2:
专利在计时电路和处理单元之间建立了双向反馈机制。错误检测电路不仅监测时间信号的生成，还接收来自处理单元的确认信号，形成闭环验证系统。这种反馈机制确保了时间同步的准确性，同时通过智能化的错误处理减少了不必要的系统复位，降低了整体复杂性
3Speed
If a parallel time bus is used to transmit system time signals, then the speed and reliability of time distribution is improved, but the power consumption and device complexity increase
Solution Approach 1:
专利采用周期性的时间信号传输机制，计时电路按照固定的时间间隔通过并行时间总线广播时间基准值，而不是持续传输。这种周期性动作在保证各处理单元能够及时同步的同时，显著降低了相比持续传输模式下的功耗，同时维持了高速同步的能力
Solution Approach 2:
并行时间总线被设计为具有冗余的传输能力和比最小需求更高的带宽。这种过度设计使得系统可以在保持高速传输能力的同时，通过智能激活策略（仅在实际需要更新时激活总线）来降低功耗，而不是始终保持最大性能状态
Data Source
AI summary
A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.