Time Code Display System Synchronization for Non-Homologous Video Signals

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Solution Overview

Problem

Traditional monitor display systems delay time code output based on cache frames or frame rate conversion, leading to inconsistencies in time code display for non-homologous video signals with different clock domains.

Innovation Solution

A time code display system comprising a video receiver, time code parser, write controller, synchronous clock component, and read controller that synchronously writes and reads video frames and time code data into and from a buffer, ensuring consistent display across multiple non-homologous video signals by generating a local clock signal and performing frame synchronization and conversion operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If time codes are output according to cache frames or frame rate conversion, then video display can be maintained, but time code display accuracy and synchronization are compromised

Engineering Contradiction:
Improvetime code display accuracyVSAvoidtime code delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-storing time code data in a buffer memory before the actual display moment. The time code parser extracts time code data from video signals in advance, and the write controller stores this data in the buffer along with video frames, enabling synchronous retrieval and display without delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer acts as an intermediary component between the time code parser and the display output. It decouples the time code extraction process from the display process, allowing time code data to be stored and retrieved synchronously with video frames, thereby eliminating the delay inherent in traditional cache-based systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If separate storage of time codes and video frames is used, then system complexity is reduced, but synchronization between time codes and video frames is lost

Engineering Contradiction:
Improvetime code-video synchronizationVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system merges time code data with video frame data in the buffer memory. The write controller stores both time code data and video frames in the same buffer structure, and the read controller retrieves them together, ensuring they remain synchronized throughout the display process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The buffer serves multiple functions: it stores video frames, stores time code data, enables synchronous reading of both, and facilitates frame rate conversion. This multi-functional approach maintains synchronization without requiring separate complex synchronization mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If frame rate conversion is applied, then video compatibility is improved, but time code consistency across different clock domains is compromised

Engineering Contradiction:
Improvevideo signal compatibilityVSAvoidtime code consistency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary time code extraction and storage in the buffer before frame rate conversion occurs. The time code parser extracts time code data from incoming video signals, and the write controller stores this data in the buffer along with the video frames, enabling consistent time code display even after frame rate conversion is applied.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer acts as an intermediary that preserves time code consistency during frame rate conversion. It stores time code data independently of the frame rate conversion process, allowing the system to convert frame rates while maintaining accurate and consistent time code display across different clock domains.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11587274B2Time code display system and method, displaying device, storage medium and electronic apparatus
Publication Date: 2023.02.21 BOE TECHNOLOGY GROUP CO LTD
  • US11587274B2 patent drawing
  • US11587274B2 patent drawing
  • US11587274B2 patent drawing

AI summary

A time code display system comprising: a video receiver configured for receiving a plurality of non-homologous video signals; a time code parser connected with the video receiver and configured for extracting time code data of each video frame from each video signal; a write controller and a buffer, the write controller being connected with the video receiver and the time code parser; a synchronous clock component configured for generating a local clock signal according to a channel associated clock signal of any video signal; and a read controller and a display, the read controller being connected with the synchronous clock component and the buffer and configured for reading out the video frame of each video signal and the time code data corresponding to the video frame from the buffer at the same time, according to the local clock signal.