Time-Continuous Pipeline ADC for High-Resolution Fast Sampling
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Solution Overview
Problem
Current Sampled Pipeline Subranging Converter (SPSC) ADCs face limitations in achieving high-resolution conversion at fast rates due to noise introduced by track-and-hold elements, which limits achievable resolution and introduces wideband noise that aliases into the sampling process.
Innovation Solution
Implementing a time-continuous pipeline ADC with a configuration that includes a delay element, a Low-Pass filter, and an anti-alias filter to minimize differences between the analog input and the output of the Digital-to-Analog Converter (DAC), thereby reducing noise and high-frequency mirrors, and using over-sampling when necessary to match frequency-dependent amplitude attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If track-and-hold elements are used in each stage of the pipeline ADC, then the converter can operate at high sampling rates, but noise is introduced that limits achievable resolution
Solution Approach 1:
The patent removes track-and-hold elements from the pipeline stages, extracting the noise-generating components while maintaining the sampling rate capability through alternative architecture design. The input stage performs the sampling function without requiring track-and-hold elements in subsequent stages.
Solution Approach 2:
The converter is divided into distinct functional stages: an input stage that handles sampling and a pipeline stage that performs conversion. This segmentation allows the sampling function to be isolated from the conversion stages, eliminating the need for track-and-hold elements in each stage while maintaining high sampling rates.
2Productivity
If track-and-hold elements are used, then sampling can be performed, but wideband noise aliases into the sampling process
Solution Approach 1:
The patent uses oversampling to push quantization noise and wideband noise to higher frequencies where they do not alias into the signal band. By sampling at a rate significantly higher than the Nyquist rate, the harmful noise is distributed over a wider frequency range, and subsequent filtering removes the aliased components.
Solution Approach 2:
An anti-alias filter is introduced as an intermediary component between the sampling stage and the pipeline converter. This filter removes wideband noise and high-frequency components before they can alias into the signal band, preventing the harmful effect while maintaining sampling capability.
3Measurement precision
If more pipeline stages are added to increase resolution, then conversion precision improves, but the complexity of the converter increases
Solution Approach 1:
The patent resolves the complexity issue by moving from a traditional multi-stage pipeline with track-and-hold elements to an architecture that uses oversampling in the time dimension. Instead of adding more complex stages, the system achieves higher resolution by sampling at higher rates and using digital signal processing techniques.
Data Source
AI summary
A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output. The digital output of the time continuous converter may be calculated by combining the digital outputs of the various sections.