Time to Current Converter with Dynamic Delay Multiplication
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Solution Overview
Problem
Existing time to current converters for integrated circuits have limitations such as low measurement resolution, insufficient timing range, and complex calibration processes, making it difficult to accurately measure small signal delays, which can occupy significant area on the chip.
Innovation Solution
A time to current converter that uses time amplification by closing switches to multiply the delay introduced by a device under test, allowing for improved delay measurement accuracy through a circuit structure involving logic gates and capacitors, enabling high-resolution measurements with reduced error and simplified calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time to current converters are used, then the device can measure signal delay, but the measurement resolution is low and timing range is insufficient
Solution Approach 1:
The patent employs dynamic delay multiplication by controlling switches to replicate delay elements conditionally. The delay path is dynamically extended through switch-controlled capacitor connections, allowing the same physical circuit to provide different effective delay ranges based on switch states, thereby resolving the contradiction between measurement precision and timing range adaptability.
Solution Approach 2:
The patent implements nested delay structures where delay elements are arranged in hierarchical levels. Each level contains delay elements that can be selectively activated, creating a nested configuration where smaller delay units are contained within larger delay paths. This nesting allows fine-grained measurement resolution at lower levels while providing extended timing range through cumulative delays at higher levels.
2Measurement precision
If conventional delay measurement devices are used, then signal delay can be measured, but the device occupies significant area on the integrated circuit
Solution Approach 1:
The patent uses dynamic switching to activate different delay paths only when needed for measurement. During normal operation, switches remain in a default state, and during measurement mode, switches reconfigure the circuit to create extended delay paths. This dynamic approach allows high-precision delay measurement capability without permanently occupying the chip area required for multiple parallel delay elements.
Solution Approach 2:
The patent divides the delay measurement function into segmented, reusable delay elements that can be selectively activated. Instead of implementing a single large delay circuit, the patent creates multiple smaller delay segments that can be combined through switching. This segmentation reduces the area occupied by any single delay element while maintaining the capability for high-precision measurement through selective activation of segments.
3Measurement precision
If conventional time to current converters are used, then delay measurement can be performed, but the calibration process is complicated
Solution Approach 1:
The patent implements self-calibration through symmetric circuit design where matching delay elements automatically compensate for process variations. The circuit structure includes paired delay paths with identical topology and component types, ensuring that systematic errors cancel out during differential measurement. This self-service approach eliminates the need for external calibration equipment and complex manual calibration procedures while maintaining high measurement accuracy.
Solution Approach 2:
The patent incorporates feedback mechanisms where the output current is compared against reference levels and used to adjust measurement parameters. The converter provides feedback about the measured delay to control logic that can compensate for non-ideal behaviors. This feedback loop simplifies calibration by allowing the system to automatically correct for minor variations without requiring precise manual adjustment of each component.
Data Source
AI summary
A device comprising a device under test and a time to current converter configured to be coupled to the device under test. The device under test comprises: (i) at least one delay element for creating a delay; (ii) at least one capacitor for providing capacitance loading to the at least one delay element; and (iii) at least one switch to control the capacitance loading provided by the at least one capacitor. The time to current converter comprises (i) a first input for receiving a first clock signal; (ii) a second input for receiving an inverted and delayed version of the first clock signal from the device under test; and (iii) an impedance module for measuring an output current. During a testing mode, the at least one switch is in a closed position so the at least one capacitor can provide a capacitance loading to the at least one delay element to amplify the delay associated with the device under test.


