Time-Decoupled Writes in Non-Linear Polar Memory Cells
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Solution Overview
Problem
The challenge of reliable programming in memory bit-cells due to reduced effective voltage across capacitors in low power applications, leading to unreliable switching of states.
Innovation Solution
Implementing a time-decoupled write operation for bit-cells using non-linear polar materials like ferroelectric or paraelectric materials, where the access transistor is operated at a voltage higher than the nominal supply voltage, and write operations for logic 0 and logic 1 are performed in different phases, ensuring fully saturated electric displacement and polarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is lowered for low power applications, then power consumption is reduced, but effective voltage across the capacitor during write operation is lowered resulting in unreliable programming
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit-line to a voltage higher than the nominal supply voltage (e.g., Vdd + Vth) before the write operation. This preliminary voltage preparation ensures that when the word-line is activated, the capacitor receives sufficient voltage (Vdd + Vth - Vth = Vdd) to achieve reliable programming even though the supply voltage is lowered for low power operation. The preliminary charging action resolves the contradiction by preparing the necessary voltage condition in advance.
Solution Approach 2:
The patent changes the voltage parameter of the bit-line from the nominal supply voltage to a boosted voltage (Vdd + Vth or higher) during the write operation. This parameter change allows the capacitor to experience the higher voltage needed for reliable programming while the rest of the system operates at the lower nominal supply voltage, thus achieving both low power consumption and high programming reliability.
2Reliability
If access transistor is operated at higher voltage than nominal supply voltage, then capacitor programming reliability is improved, but transistor stress and potential breakdown increase
Solution Approach 1:
The access transistor is pre-biased at a higher voltage (Vdd + Vth) before the write operation through preliminary charging of the bit-line. This preliminary action allows the transistor to operate at the higher voltage only when needed for capacitor programming, rather than continuously, thereby reducing cumulative stress and potential breakdown while ensuring reliable programming when the operation is performed.
Solution Approach 2:
The high voltage operation of the access transistor is applied periodically or selectively only during write operations rather than continuously. The bit-line is charged to the higher voltage (Vdd + Vth) temporarily during write operations and then returned to the nominal supply voltage for read operations and standby, creating a periodic high-stress pattern that minimizes cumulative damage while achieving reliable programming when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances storage endurance by achieving reliable switching of states in capacitors, reducing variations in electric displacement and polarization, and preventing oxide breakdown and electromigration effects.
Implementation Method 1
capacitor with non-linear polar material such as ferroelectric material, paraelectric material, or non-linear dielectric
Implementation Method 2
capacitor with non-linear polar material such as ferroelectric material, paraelectric material, or non-linear dielectric
Implementation Method 3
behavior of a ferroelectric capacitor, a paraelectric capacitor, and a linear capacitor
Data Source
AI summary
Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.