Time Detection Circuit Latch Control for Low Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing time detection circuits face challenges in reducing current consumption, particularly in applications like digital still cameras, where high-frequency operations lead to increased power usage due to the continuous operation of latch circuits.
Innovation Solution
The proposed solution involves a time detection circuit with a latch unit that operates only during specific timings, enabled by a second pulse and performing a latch at a predetermined time after the second timing, along with an annular delay circuit and a comparison unit, to reduce the overall current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the latch circuit operates continuously at high frequency, then the time detection accuracy is improved, but the current consumption increases
Solution Approach 1:
The latch circuit is designed to operate periodically rather than continuously. It is enabled only during specific timing windows when data latching is required, and remains disabled during other periods. This periodic operation maintains time detection accuracy when needed while significantly reducing average current consumption.
Solution Approach 2:
The latch circuit's operational state is dynamically controlled through an enable signal. The circuit transitions between enabled and disabled states based on timing requirements, allowing it to adapt its operation to actual needs rather than running continuously at fixed high frequency.
2Reliability
If the latch unit operates for longer duration, then the data latching reliability is improved, but the power consumption increases
Solution Approach 1:
The latch circuit is enabled in advance of the actual data latching moment. The enable signal is activated before the data arrives, ensuring the latch circuit is ready to capture the data reliably, then disabled after latching completes. This preliminary enabling ensures reliability while limiting power consumption to only the necessary window.
Data Source
AI summary
A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.