Time-Deterministic Microprocessor Architecture for Jitter-Free Execution
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Solution Overview
Problem
Conventional processor architectures fail to provide deterministic and high-precision command execution with low microsecond-range repetition times, especially in complex measurement systems requiring precise synchronization of actuators, sensors, and computing units, due to limitations in temporal determinism and interrupt handling.
Innovation Solution
A microprocessor architecture with a time management unit that discretizes time into system cycles, allowing each instruction to specify its execution time, ensuring that commands are executed within a predetermined system cycle, providing deterministic and jitter-free temporal behavior across the processor logic and peripheral modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processor architectures are used, then flexibility in program execution is maintained, but temporal determinism and precision in command execution deteriorate
Solution Approach 1:
The processor architecture is segmented into distinct functional units: a time management unit that handles timing/discretization, an instruction execution unit that processes commands, and a buffer memory unit that stores instructions with time specifications. This segmentation allows each unit to specialize in its function, achieving temporal determinism without requiring complete redesign of the entire processor.
Solution Approach 2:
The time management unit acts as an intermediary between the instruction execution unit and the buffer memory. It receives instructions with time specifications from memory, discretizes time into system cycles, and schedules instruction execution accordingly. This intermediary component enables temporal determinism by mediating the execution timing without requiring complex changes to the core processor architecture.
2Speed
If interrupt handling is used for event response, then system responsiveness is improved, but execution time variability and jitter increase
Solution Approach 1:
The system uses periodic system cycles as the basis for instruction execution timing. Instead of relying on asynchronous interrupts that cause variable execution times, the time management unit creates regular, periodic time intervals (system cycles) and schedules instruction execution to occur at predetermined points within these cycles. This periodic structure ensures that execution times remain deterministic while maintaining system responsiveness through regular polling or scheduled event handling.
3Measurement precision
If time discretization into system cycles is implemented, then command execution precision is improved, but overhead in time management increases
Solution Approach 1:
The time management unit operates autonomously to discretize time and schedule instruction execution without requiring continuous intervention from the instruction execution unit or external controllers. Once the system cycles are established, the time management unit automatically manages the scheduling and timing of instructions, reducing the computational overhead on the main processor while maintaining high timing precision.
Data Source
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AI summary
Microprocessor or microcontroller (1), comprising at least one memory (2) for holding instructions (4), at least one instruction loading unit (3) and at least one instruction execution unit (5), wherein the instruction loading unit (3) is designed to retrieve instructions (4) from the memory (2) and to transmit them to the instruction execution unit (5), wherein each instruction (4) contains at least one command (4a) and a time stipulation (4b) and wherein the instruction execution unit (5) is designed to execute the command (4a), wherein there is additionally provision for a time management unit (6) designed to prescribe a system clock (71), consisting of a sequence of system cycles (71a, 71b), and to signal at least the beginning of each system cycle (71a, 71b) to the instruction execution unit (5), wherein each system cycle (71a, 71b) comprises a plurality of cycles (70a, 70b) of the processor clock (70) of the microprocessor or microcontroller (1), wherein the time stipulation (4b) in the respective instruction (4) indicates the system cycle (71a, 71b) for which the execution of the command (4a) is planned, and wherein the instruction execution unit (5) is designed to respond to the signalling of the beginning of a system cycle (71a, 71b) by executing all commands (4a) whose execution is planned for this system cycle (71a, 71b) within this system cycle (71a, 71b).