Time-Difference Adder Circuits for Low-Voltage TDC Precision
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Solution Overview
Problem
As design rules and power supply voltages decrease, the signal-to-noise ratio (SNR) in voltage signals deteriorates, leading to performance issues in analog-to-digital converters (ADCs), prompting the need for alternative converters that can effectively process time differences in digital signals.
Innovation Solution
A system-on-chip (SOC) incorporating a time difference adder and accumulator, along with a sigma-delta time-to-digital converter, which adds and accumulates time differences between input signals to generate digital outputs, improving signal processing in low-power environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If design rules and power supply voltage decrease, then device scaling and power consumption improve, but signal-to-noise ratio of voltage signals deteriorates
Solution Approach 1:
The patent replaces voltage-domain signal processing with time-domain signal processing. Instead of using voltage signals that suffer from noise when power supply decreases, the invention uses time-interleaved signal paths where the timing differences between signals are measured and converted to digital values. This substitution of the signal domain (from voltage to time) resolves the contradiction by making signal processing immune to voltage noise while maintaining compatibility with low-power design rules.
Solution Approach 2:
The invention changes the fundamental parameter used for signal representation from voltage amplitude to time delay. By measuring the time difference between corresponding edges of interleaved signals and converting this temporal information to digital values, the system maintains high signal-to-noise ratio even when power supply voltage decreases, thus resolving the contradiction between low power consumption and measurement precision.
2Measurement precision
If analog-to-digital converter performance deteriorates due to low voltage, then conversion accuracy decreases, but switching to time-to-digital converter improves signal processing
Solution Approach 1:
The patent divides the signal processing into multiple parallel time-interleaved paths, each processing a different phase of the input signal. By segmenting the conversion process across multiple parallel channels and then combining their time difference measurements, the system achieves high conversion accuracy without relying on high-voltage analog processing, thus improving measurement precision while managing device complexity through modular architecture.
Solution Approach 2:
The invention substitutes analog voltage-based conversion with digital time-based conversion. Instead of using complex analog-to-digital conversion circuits that degrade at low voltage, the system uses time-to-digital conversion that measures temporal relationships between signals. This substitution improves conversion accuracy in low-power environments by eliminating the voltage-dependent noise issues inherent in analog conversion.
Data Source
AI summary
A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.