Time Difference Adjustment Circuit for Sub-Inverter Signal Delay
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Solution Overview
Problem
Conventional time difference adjustment circuits, such as those using inverter chains, face challenges in providing signal delays smaller than the inverter delay, making it difficult to effectively adjust the time difference between input signal edges, which is crucial for signal processing in low-voltage LSIs.
Innovation Solution
A time difference adjustment circuit utilizing flip-flop circuits, a delay circuit with cascade-connected minimum-delay units comprising NMOS and PMOS transistors, and a reset circuit to achieve a delay amount smaller than the inverter delay, allowing for precise time difference adjustment between input signal edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an inverter chain is used as a delay circuit, then the circuit structure is simple, but the minimum delay amount is limited to one inverter delay
Solution Approach 1:
The delay circuit is divided into multiple minimum-delay units (first and second types) that can be cascade-connected. Each unit contains transistors configured to provide minimal delay, and by connecting multiple units in series, the circuit achieves fine-grained time difference adjustment while maintaining simple individual unit structures.
Solution Approach 2:
The circuit uses flip-flop circuits with reset functionality to dynamically control the delay amount. The reset circuit detects edges of delayed and non-delayed signals and generates reset signals to clear the flip-flops, enabling dynamic adjustment of the time difference between input signal edges with resolution finer than a single inverter delay.
2Measurement precision
If the delay amount is reduced below inverter delay, then time difference adjustment precision is improved, but circuit complexity increases
Solution Approach 1:
The delay circuit is segmented into multiple minimum-delay units that can be cascade-connected. Each unit provides a minimal delay increment, and by combining multiple units, the circuit achieves fine time difference adjustment precision without requiring a single complex high-precision delay element.
Solution Approach 2:
The reset circuit automatically detects the edges of both delayed and non-delayed signals and generates appropriate reset signals to clear the flip-flops, enabling self-adjusting time difference measurement with precision better than a single inverter delay without requiring external control logic.
3Use of energy by moving object
If conventional delay circuits are used, then power consumption is higher due to through current, but the circuit is easier to design
Solution Approach 1:
The circuit converts the potential harmful through current in conventional delay circuits into a beneficial feature by using the reset mechanism. The reset circuit detects signal edges and clears flip-flops to prevent through current, thereby reducing power consumption while maintaining simple circuit design through the use of standard flip-flop and transistor components.
Data Source
AI summary
A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors.