Time-to-Digital Converter Using Latched State Transitions

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Solution Overview

Problem

Existing time to digital converters face complexity and high-speed operation challenges due to the need for counters to count short time intervals, leading to complicated configurations and increased power consumption.

Innovation Solution

A time to digital converter design that includes a state transition section, a transition-state acquiring section, and an arithmetic operation section, where the state transition section transitions based on a trigger signal, the transition-state acquiring section synchronizes and holds state information, and the arithmetic operation section calculates a time digital value by weighting and integrating the number of state transitions, with options to set upper limits and stop transitions, reducing the need for high-speed counters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a counter is used to count the number of cycles of the state transition section for measuring short time intervals, then the measurement precision is improved, but the device complexity increases due to the need for a complicated high-speed counter configuration

Engineering Contradiction:
Improvetime interval measurement precisionVSAvoidconverter configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the time interval measurement into two segments: a coarse measurement from a general counter and a fine measurement from the latched state of the ring oscillator. This segmentation allows the use of a simple counter for coarse measurement while using the ring oscillator's natural state transitions for fine measurement, avoiding the need for a complex high-speed counter while maintaining high precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a latch circuit as an intermediary between the ring oscillator and the counter. The latch captures the state of the ring oscillator at the end of the input pulse, allowing the system to measure time intervals without requiring the counter to operate at the high frequency of the ring oscillator, thus simplifying the counter configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If a complicated high-speed counter is used to count short time intervals, then the productivity is improved, but the power consumption increases

Engineering Contradiction:
Improveconversion speedVSAvoidconverter power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The measurement function is segmented between a low-power counter for coarse measurement and a high-frequency ring oscillator for fine measurement. The counter operates at lower speed and consumes less power, while the ring oscillator's state transitions provide the high-resolution timing information needed for fast conversion without requiring the counter to run at high speed continuously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ring oscillator serves itself by using its own internal state transitions to provide the fine measurement information. The latch circuit captures the oscillator's state at the measurement endpoint, allowing the system to obtain high-resolution timing data without requiring external high-speed counting mechanisms, thereby reducing overall power consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10972116B2Time to digital converter and A/D conversion circuit
Publication Date: 2021.04.06 SEIKO EPSON CORP
  • US10972116B2 patent drawing
  • US10972116B2 patent drawing
  • US10972116B2 patent drawing

AI summary

There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a cycle in which the state information held by the transition-state acquiring section is updated.