Time-to-Digital Conversion Circuit With Phase Selection for Low Latency
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Solution Overview
Problem
Conventional time-to-digital converters face challenges with high latency, circuit scale, and power consumption due to the need for multiple latch circuits and comparators, as well as increased latency and circuit complexity from delay units inserted to prevent signal passing before phase comparison results are determined.
Innovation Solution
A time-to-digital conversion circuit that includes a phase comparator, a phase selector, and a delay unit, where the phase selector distinguishes between leading and lagging phases without waiting for phase comparison results, and the delay unit outputs the leading phase with a delay, eliminating the need for additional delay units, and featuring symmetric NAND and NOR circuits and a time difference amplifier to improve input/output characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay units are inserted in each input signal path to prevent signals from passing through before phase comparison results are determined, then signal passing is prevented, but latency increases
Solution Approach 1:
The phase selector performs preliminary action by identifying and selecting the leading phase signal before the phase comparison result is fully determined. This allows the system to prepare the delayed signal path in advance, eliminating the need for additional delay units and reducing overall latency while still preventing premature signal passing.
2Measurement precision
If multiple latch circuits and comparators are used to generate n-bit digital code, then conversion accuracy is improved, but circuit scale increases
Solution Approach 1:
The time-to-digital conversion process is segmented into multiple stages, with each stage handling a portion of the conversion. The phase selector and delay unit work together in a cascaded structure where each stage processes a specific bit position, reducing the complexity at each individual stage while maintaining overall conversion accuracy through the coordinated operation of all stages.
3Measurement precision
If multiple latch circuits and comparators are used to generate n-bit digital code, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The conversion process is divided into multiple stages, each handling a specific portion of the conversion task. This segmentation allows power to be distributed across stages rather than concentrated in a single complex circuit, reducing peak power consumption while maintaining overall conversion accuracy through the cumulative operation of all stages.
4Reliability
If delay units are inserted in each input signal path, then signal passing is prevented, but circuit scale increases
Solution Approach 1:
The phase selector and delay unit are merged into an integrated functional block that performs both phase selection and signal delay operations. This consolidation eliminates the need for separate delay units in each signal path, reducing the overall circuit scale while maintaining the ability to prevent premature signal passing through the integrated control mechanism.
Data Source
AI summary
A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.