Time-Division CAM Control for Peak Current Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional content addressable memory (CAM) arrays face electromigration (EM) and voltage variation (IR) issues due to shared power and ground lines, leading to reduced chip lifespan and performance, as well as high power consumption when all match output units are activated simultaneously.

Innovation Solution

A time-division memory control device is introduced, featuring a time-division controller that generates staggered control signals to manage the operation of CAM cell arrays, dividing peripheral circuits into groups to coordinate operations in a time-division manner, thereby reducing peak current and mitigating EM/IR problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all match output units are activated simultaneously, then the CAM array can process multiple search operations in parallel, but power consumption increases and EM/IR problems occur

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the CAM array into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3) and activates only one bank at a time during search operations. This segmentation allows parallel processing capability to be maintained across different time slots while reducing instantaneous power consumption and avoiding EM/IR problems that would occur if all units were activated simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic activation of different CAM banks using control signals (e.g., bank select signals BS0-BS3) that enable one bank at a time in a sequential manner. This periodic action maintains the overall parallel processing throughput while ensuring that power consumption and current density remain within safe limits at any given moment.

Inventive Principle:
Principle #19Periodic action

2Area of stationary object

If power and ground lines are shared among adjacent CAM cells to reduce layout area, then area efficiency improves, but electromigration and voltage variation problems increase

Engineering Contradiction:
Improvelayout areaVSAvoidEM/IR problem severity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the CAM array into multiple independent banks, each with its own dedicated power and ground lines. This segmentation prevents the EM/IR problems that would arise from sharing power and ground lines across the entire array, as each bank's power consumption is isolated and controlled, while still achieving area efficiency through the overall compact bank structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent provides different power and ground line configurations for different banks. Specifically, odd-numbered banks (Bank 1, Bank 3) use VDDP/VSSP power and ground lines, while even-numbered banks (Bank 0, Bank 2) use VDD/VSS power and ground lines. This local differentiation ensures that power consumption patterns in one bank do not interfere with adjacent banks, mitigating EM/IR problems while maintaining area efficiency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11861213B2Time-division memory control device
Publication Date: 2024.01.02 REALTEK SEMICON CORP
  • US11861213B2 patent drawing
  • US11861213B2 patent drawing
  • US11861213B2 patent drawing

AI summary

A time-division memory control device controls a content addressable memory (CAM) cell array of a CAM in a time-division manner and thereby reduces a peak current and mitigates electromigration and voltage variation problems. The time-division memory control device includes a time-division controller and a peripheral circuit. In a search and compare operation, the time-division controller outputs a first group of control signals at a first time point according to a system clock, and outputs a second group of control signals at a second time point later than the first time point. The peripheral circuit includes: a first group of circuits cooperating with a first group of CAM cells of the CAM cell array according to the first group of control signals; and a second group of circuits cooperating with a second group of CAM cells of the CAM cell array according to the second group of control signals.