Time-Domain ADC Clocking to Cut Conversion Delay and Power
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Solution Overview
Problem
Voltage domain analog-to-digital converters experience delays due to settling time of capacitors and decision time of comparators, leading to inefficiencies in converting analog input voltages to digital signals.
Innovation Solution
A time domain analog-to-digital converter employing a plurality of stages that operate sequentially, utilizing clock generating circuits to decide bits based on positive and negative pulses, reducing waiting times and power consumption through pipelined successive-approximation and flash TDC circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage domain ADC is used to convert analog input voltage to digital signal, then conversion accuracy is achieved, but conversion time increases due to settling time of capacitor and decision time of comparator
Solution Approach 1:
The patent replaces the voltage domain conversion mechanism with a time domain conversion mechanism. Instead of using capacitors and comparators in the voltage domain, the invention uses time-to-digital conversion circuits that operate in the time domain, thereby eliminating the settling time and comparator decision time constraints while maintaining conversion accuracy.
Solution Approach 2:
The patent changes the domain parameter from voltage to time. By converting the analog input voltage into a time interval and then converting that time interval to a digital value, the system avoids the time-consuming voltage comparison process while preserving the measurement precision through the time-based representation of the voltage magnitude.
2Reliability
If traditional voltage domain ADC is used, then reliable conversion is achieved, but power consumption increases due to continuous operation of capacitors and comparators
Solution Approach 1:
The patent employs periodic clock signals to control the time-to-digital conversion process. The conversion occurs in discrete time intervals synchronized with the clock cycles, allowing the circuit to remain in a low-power state between conversion operations while maintaining reliable conversion when activated, thus reducing overall power consumption.
3Productivity
If waiting time is reduced in ADC operation, then productivity increases, but conversion accuracy may be compromised
Solution Approach 1:
The patent substitutes the slow voltage domain conversion process with a faster time domain conversion process. The time-to-digital converter processes the time interval representation of the input voltage much faster than traditional voltage comparators can resolve voltage differences, thereby increasing productivity without sacrificing the precision that is preserved in the time-domain representation.
Data Source
AI summary
In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.