Differential Time-Domain ADC with Pulse Detection for TDC Linearity
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Solution Overview
Problem
Many time-domain analog-to-digital converters (ADCs) suffer from poor linearity when converting short time differences or durations, particularly in differential ADCs where input voltages are close to each other.
Innovation Solution
Incorporating a pulse-detector circuit connected to the outputs of voltage-to-time converters (VTCs) to ensure a minimum duration for the output pulses, which are then processed by separate time-to-digital converters (TDCs), thereby ensuring that the durations to be converted are not shorter than this minimum duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a direct time-domain conversion is used without pulse-detector circuit, then the ADC structure is simpler, but the linearity deteriorates when converting short time differences
Solution Approach 1:
The patent introduces a pulse-detector circuit as an intermediary component between the voltage-to-time converters and the time-to-digital converters. This pulse-detector circuit generates output pulses with guaranteed minimum duration by detecting the transitions of input pulses from VTCs and controlling the timing of output pulse generation and termination, thereby ensuring sufficient pulse width for accurate TDC conversion while maintaining the overall ADC architecture.
2Measurement precision
If the pulse-detector circuit is added to ensure minimum pulse duration, then the linearity of short time difference conversion is improved, but the device complexity increases
Solution Approach 1:
The patent segments the ADC functionality into distinct modules: voltage-to-time converters, a pulse-detector circuit, and time-to-digital converters. The pulse-detector circuit itself is segmented into transition detection logic and output pulse generation control logic. This segmentation allows each component to perform its specific function efficiently while maintaining modularity and manageability of the overall system complexity.
Solution Approach 2:
The pulse-detector circuit serves as an intermediary that bridges the VTC and TDC stages, adding value by ensuring minimum pulse duration without requiring fundamental changes to the existing VTC or TDC architectures, thus limiting the increase in overall system complexity.
3Measurement precision
If the pulse-detector circuit components are designed for longer minimum duration, then the TDC linearity is improved, but the loss of time in pulse generation increases
Solution Approach 1:
The pulse-detector circuit dynamically adjusts the output pulse duration based on the actual input signal characteristics. Rather than using fixed long-duration pulses that would always incur time loss, the circuit generates the minimum necessary pulse duration required for accurate TDC conversion, adapting to each conversion cycle's requirements and thus minimizing unnecessary time delays.
Solution Approach 2:
The patent changes the parameter of pulse duration from a fixed long value to a dynamically determined minimum value. The pulse-detector circuit controls the output pulse width to be just sufficient for TDC linearity requirements, adjusting this parameter based on the specific conversion needs rather than using a conservative fixed value, thereby reducing time loss while maintaining measurement precision.
Data Source
AI summary
An ADC (50) is disclosed. It has two VTCs (110a, 110b) for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit (120) coupled to outputs (114a, 114b) of the two VTCs (110a, 110b). The pulse-detector circuit (120) is configured to make a transition from a first logic state (‘0’) to a second logic state (‘F) at a first output (124a) of the pulse-detector circuit (120) in response to the start of the pulse from one of the VTCs (110a) and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output (124b) of the pulse-detector circuit (120) in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit (120) is configured to reset both the first and the second output (124a, 124b) to the first logic state (‘0’) in response to both the first output (124a) and the second output (124b) of the pulse-detector circuit (120) being set in the second logic state (‘1’). The ADC (50) further has a first TDC (130a) coupled to the first output (124a) of the pulse-detector circuit (120) and a second TDC (130b) coupled to the second output (124b) of the pulse-detector circuit (120).