Time Domain Discrete Transform Computation Using Pulse Width Signal Integration
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Solution Overview
Problem
Conventional systems for performing Discrete Transforms, such as the Walsh Transform, require high power consumption and extensive processing operations due to the need for analog-to-digital conversion and large arithmetic blocks, memory space, and die area usage.
Innovation Solution
A system and method that perform Discrete Transforms directly on pulse width signals in the time domain using parallel counters, synchronizers, and accumulators, eliminating the need for time-to-digital conversion and reducing processing operations, arithmetic blocks, and power consumption by integrating increment signals to generate frequency domain signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional systems use analog-to-digital conversion and large arithmetic blocks for Discrete Transforms, then transform computation can be performed, but power consumption increases and processing complexity increases
Solution Approach 1:
The patent extracts and eliminates the analog-to-digital conversion stage from the transform computation system. By operating directly on pulse width signals in the time domain, the system removes the power-consuming ADC and subsequent digital processing stages, achieving transform computation with significantly reduced power consumption while maintaining computational accuracy
Solution Approach 2:
The patent replaces complex digital arithmetic blocks with simpler counter-based time domain processing. Instead of using large arithmetic units for digital computation, the system uses counters to accumulate pulse width signals directly, substituting mechanical/digital computation with a more efficient time-domain signal integration approach
2Measurement precision
If conventional systems use large arithmetic blocks and memory space for Discrete Transforms, then transform computation can be performed, but die area increases
Solution Approach 1:
The patent removes the need for large arithmetic blocks and extensive memory space by eliminating the analog-to-digital conversion stage. The time domain direct processing approach requires minimal storage for pulse width signals and uses simple counter circuits instead of complex arithmetic units, dramatically reducing die area while preserving transform computation capability
Solution Approach 2:
The patent uses simple counter circuits that require minimal hardware resources compared to large arithmetic blocks. The counters are lightweight, low-complexity components that perform the necessary accumulation function without requiring extensive die area, effectively replacing expensive, area-intensive digital computation hardware
3Measurement precision
If conventional systems perform Discrete Transforms with large arithmetic blocks, then transform computation can be performed, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex analog-to-digital conversion and digital arithmetic processing stages from the system. By operating directly on pulse width signals using simple counters, the device complexity is dramatically reduced while maintaining the ability to perform accurate transform computations through time domain integration
Solution Approach 2:
The patent replaces complex digital arithmetic blocks with simple counter-based time domain processing. This substitution eliminates the need for sophisticated digital signal processing hardware, reducing device complexity to basic signal accumulation and integration operations that are much easier to implement and control
Data Source
Figure 1~2A
Figure 2B
Figure 3
AI summary
In accordance with embodiments, a first counter of a plurality of counters of an apparatus receives a plurality of pulse width signals in the time domain. The first counter generates a first increment signal in the time domain from the plurality of pulse width signals based on a first row of a Discrete Transform matrix. A synchronizer of the apparatus receives the first increment signal. The synchronizer generates a first synchronized increment signal in the time domain from the first increment signal. A first accumulator of a plurality of accumulators of the apparatus receives the first synchronized increment signal. The first accumulator accumulates the first synchronized increment signal over a period of time to generate a first frequency domain signal.