Time-Domain Multiply-Accumulate Circuit for Neural Network Efficiency

Solution Overview

Problem

Conventional digital operation methods for neural networks, such as convolutional neural networks, face challenges with high power consumption and large occupied area due to numerous multiply-accumulate operations, limiting their application in real-time systems.

Innovation Solution

A multiply-accumulate calculation method and circuit that includes a multiplication calculation circuit array and an accumulation calculation circuit, utilizing cascaded multiplication circuits, selection-shift units, and a delay accumulation circuit to perform operations in a time domain, optimizing power consumption and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional digital operation methods are used for multiply-accumulate operations in neural networks, then calculation accuracy can be maintained, but power consumption increases and occupied area expands

Engineering Contradiction:

Improvecalculation accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces conventional digital multiplication circuits with a time-domain analog multiplication approach using delay elements and accumulation circuits. Instead of using traditional digital multipliers that consume high power and occupy large area, the invention uses a time-quantization method where multiplication is achieved through controlled delay and accumulation of signals, significantly reducing power consumption and circuit area while maintaining calculation accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational domain from spatial (digital bit-wise multiplication) to temporal (time-domain delay and accumulation). By transforming the multiplication operation into a time-domain operation using delay elements and accumulation circuits, the system achieves the same computational result with reduced power consumption and smaller circuit footprint

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If conventional digital operation methods are used for multiply-accumulate operations in neural networks, then calculation accuracy can be maintained, but occupied area increases

Engineering Contradiction:

Improvecalculation accuracyVSAvoidoccupied area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent replaces conventional digital multiplication circuits with a time-domain analog multiplication approach using delay elements and accumulation circuits. Instead of using traditional digital multipliers that consume high power and occupy large area, the invention uses a time-quantization method where multiplication is achieved through controlled delay and accumulation of signals, significantly reducing power consumption and circuit area while maintaining calculation accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent merges multiple multiplication and accumulation operations into a unified time-domain processing structure. By cascading delay elements and accumulation circuits, the system performs multiple multiply-accumulate operations in sequence through time-division multiplexing, reducing the total circuit area compared to implementing separate digital multipliers for each operation

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by moving object

If time-domain accumulation with TDC circuit is used, then power consumption is reduced, but conversion complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent replaces conventional digital multiplication circuits with a time-domain analog multiplication approach using delay elements and accumulation circuits. Instead of using traditional digital multipliers that consume high power and occupy large area, the invention uses a time-quantization method where multiplication is achieved through controlled delay and accumulation of signals, significantly reducing power consumption and circuit area while maintaining calculation accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10984313B2Multiply-accumulate calculation method and circuit suitable for neural network

Publication Date: 2021.04.20 SOUTHEAST UNIV

AI summary

The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.