Time-Domain Assist SAR ADC Using TDC and Delayed TVC
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Solution Overview
Problem
High-speed analog to digital converters (ADCs) face challenges in maintaining energy efficiency and requiring complex calibration due to unpredictable gain in power-sensitive open-loop dynamic residue amplifiers, especially in pipelined and hybrid architectures.
Innovation Solution
Employing a time-domain sampler with a time-to-digital converter (TDC) as an assist quantizer, delaying the input signal to use a slower, more power-efficient TDC instead of a high-power flash ADC, and incorporating a current integrating dynamic amplifier for tunable gain, along with a shared delay line to reduce calibration requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a flash ADC is used as an assist quantizer to improve sampling speed, then the coarse estimate bits are ready in time for SAR sampling, but power consumption grows exponentially with the number of bits
Solution Approach 1:
The ADC is divided into two functional segments: a flash-based assist quantizer for coarse estimation and a SAR ADC for fine quantization. This segmentation allows the system to use the speed advantage of flash ADC only for the most significant bits, while the majority of bits are converted using the power-efficient SAR approach, thus resolving the contradiction between speed and power consumption
Solution Approach 2:
The flash assist quantizer performs only partial conversion (coarse estimation of MSBs) rather than full N-bit conversion. By performing just enough action to prepare the feedback DAC for SAR operation, the system achieves the necessary speed without the exponential power cost of a full flash ADC
2Speed
If pipelining is used to improve speed by splitting conversion into multiple stages, then feedback cycles per stage are reduced, but inter-stage gain estimation and calibration are required
Solution Approach 1:
The patent extracts the gain estimation requirement from the system by using a single feedback DAC for both coarse and fine conversion. This eliminates the need for inter-stage gain estimation and calibration between separate amplification and conversion stages, reducing complexity while maintaining pipelined speed advantages
3Use of energy by moving object
If open-loop dynamic residue amplifiers are used to improve energy efficiency, then power consumption is reduced, but gain becomes unpredictable requiring calibration
Solution Approach 1:
The patent removes the calibration requirement by eliminating open-loop dynamic residue amplifiers with unpredictable gain. Instead, it uses a single feedback DAC that maintains accurate gain characteristics, allowing the system to achieve energy efficiency through SAR's sequential operation without sacrificing gain predictability
Data Source
AI summary
An apparatus, system, and method for are provided. A device includes a time-to-digital converter (TDC) situated to convert a time-domain signal to a digital value, a delay circuit situated in parallel with the TDC and to delay the time-domain signal by a specified amount of time resulting in a delayed time-domain signal, a time-to-voltage converter (TVC) situated to produce a voltage-domain signal based on the delayed time-domain signal, and a successive approximation (SAR) circuit situated to receive the digital value and the voltage-domain signal and produce a digital-domain version of the input signal.