Time-Encoded Analog Filters With DLL Delay Control

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Solution Overview

Problem

Conventional analog filters require large circuit areas due to the need for large capacitors, and they tend to increase in size with more advanced process nodes, while also being susceptible to variations caused by process, voltage, and temperature (PVT) fluctuations.

Innovation Solution

The implementation of analog filters using time encoding (TE) techniques, which employ strings of digital inverters to create delay elements, and utilize delay-locked loops (DLLs) to control filter delay, thereby reducing the impact of PVT fluctuations and improving resilience to variable conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional analog filters use large capacitors to achieve low noise and low frequency filtering, then filtering performance is improved, but circuit area increases significantly

Engineering Contradiction:
Improvefiltering performanceVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transforms the filter implementation from using large capacitors to using time encoding with digital inverters. This changes the fundamental parameter from capacitance value to time delay, allowing the same filtering function to be achieved with much smaller circuit area while maintaining low noise and low frequency performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional analog capacitor-based filtering mechanism with a digital time-encoding mechanism. Instead of using physical capacitors to store and release energy for filtering, the system uses sequences of digital inverters to create time delays that achieve the same filtering effect with minimal area.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If conventional analog filters are designed with more advanced process nodes, then manufacturing precision is improved, but device area increases

Engineering Contradiction:
Improveprocess node advancementVSAvoidcircuit area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent changes the design parameter from capacitor size (which scales with process node) to time delay achieved through digital inverter sequences. This parameter transformation allows advanced process nodes to be used without the area penalty that would normally accompany higher precision manufacturing.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If conventional analog filters operate under varying process, voltage, and temperature conditions, then adaptability is maintained, but filter characteristics vary significantly

Engineering Contradiction:
Improveoperational flexibilityVSAvoidfilter stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent incorporates delay-locked loops (DLLs) that provide feedback control to the time-encoding mechanism. The DLLs continuously monitor and adjust the delay parameters to compensate for PVT variations, maintaining stable filter characteristics while allowing the system to operate across varying process, voltage, and temperature conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent uses dynamic parameter adjustment through DLL-controlled delay elements to counteract the effects of PVT variations. By changing the delay parameters in real-time based on operating conditions, the system maintains consistent filter performance across different environmental and process variations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12323160B2Filters
Publication Date: 2025.06.03 CIRRUS LOGIC INC
  • US12323160B2 patent drawing
  • US12323160B2 patent drawing
  • US12323160B2 patent drawing

AI summary

An analog filter, comprising, a first-time encoding machine (TEM); and a first delay element.