Time-Encoded Serial Interconnect Without a Separate Clock Lane

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Solution Overview

Problem

Existing data interconnects face challenges in achieving high throughput with low energy consumption while minimizing interference and space consumption, particularly in mobile devices and other systems.

Innovation Solution

The Serial Time Encoded Phy (STEP) interconnect uses time encoding to modulate digital pulses, eliminating the need for a separate clock lane and enabling high throughput with low power requirements, utilizing differential or single-ended transmission lines for efficient data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If traditional digital interfaces like PCI-E or SATA are used, then data transfer reliability is ensured, but power consumption increases and space requirements grow

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transfer throughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent changes the fundamental parameter of data encoding from voltage-based digital signaling to time-based pulse encoding. By representing data in the temporal domain rather than voltage levels, the system achieves lower power consumption while maintaining high data transfer rates, directly resolving the contradiction between energy efficiency and throughput

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention replaces the traditional electrical voltage-based signaling mechanism with a time-based pulse encoding mechanism. This substitution eliminates the need for high-voltage switching and complex equalization circuits, thereby reducing power consumption while preserving data integrity and transfer speed

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If separate clock lanes are added for synchronization, then data transfer accuracy improves, but device complexity and space consumption increase

Engineering Contradiction:
Improvedata transfer accuracyVSAvoidinterconnect structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the data signal and clock signal into a single integrated pulse train. The regular periodic pulses inherently provide timing reference information, eliminating the need for separate clock lanes while maintaining synchronization accuracy. This consolidation reduces device complexity and space requirements

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The transmitted pulse signal serves multiple functions simultaneously: it carries data information through its timing characteristics, provides clock synchronization through its periodic nature, and enables signal integrity monitoring. This multi-functionality eliminates the need for dedicated clock infrastructure, reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If voltage-based digital signaling is used, then ease of implementation is maintained, but interference with other system components increases

Engineering Contradiction:
Improveimplementation simplicityVSAvoidelectromagnetic interference
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The invention substitutes voltage-based electrical signaling with time-based pulse encoding. This fundamental substitution reduces electromagnetic radiation and crosstalk since the signals operate at lower voltage levels while maintaining data integrity through temporal encoding, thereby reducing interference with mobile device components

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The use of periodic pulse trains with controlled duty cycles creates a more predictable and manageable signal profile. This periodic structure facilitates easier filtering and synchronization while reducing spectral spreading and interference with adjacent frequency components, maintaining implementation simplicity while reducing harmful electromagnetic effects

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3685555B1Time encoded data communication protocol, apparatus and method for generating and receiving a data signal
Publication Date: 2025.12.17 INTEL CORP
  • EP3685555B1 patent drawingFigure 1a
  • EP3685555B1 patent drawingFigure 1b
  • EP3685555B1 patent drawingFigure 1c

AI summary

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.