Time-Grid Buffer Synchronization for Deterministic Data Processing

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Solution Overview

Problem

Existing data processing systems face challenges in managing high complexity, ensuring deterministic communication, and reducing copy-free data transfer while maintaining functional safety, particularly in applications like autonomous driving and robotic systems, where large volumes of data are processed with stringent safety requirements.

Innovation Solution

A method utilizing a time grid with predetermined repetition rates and buffer memories for data processing tasks, ensuring synchronization and copy-free communication by assigning output data to specific buffer memory locations, which are accessed at predetermined clock pulses, thereby reducing complexity and ensuring deterministic communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If copy-free data transfer mechanisms are implemented to improve performance, then data processing speed increases, but system complexity increases due to dynamic memory management requirements

Engineering Contradiction:
Improvedata processing speedVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory space is segmented into dedicated buffer memory regions for different data processing tasks. Each task has predetermined input and output buffer locations, eliminating the need for dynamic memory allocation and management while enabling copy-free data transfer between tasks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Buffer memory locations are predetermined and allocated before data processing begins. This preliminary arrangement of memory spaces allows tasks to directly read and write data without runtime memory management, improving processing speed while maintaining manageable complexity through static allocation.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple data processing tasks operate in parallel to improve processing capacity, then overall system performance increases, but determining data flow and ensuring deterministic communication becomes more difficult

Engineering Contradiction:
Improveprocessing capacityVSAvoiddata flow management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Data processing tasks are organized to execute periodically at predetermined times within a time grid. This periodic execution pattern, combined with assigned buffer locations, ensures deterministic communication between tasks while enabling parallel operation to maintain high processing capacity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Buffer memories serve as intermediary structures between data processing tasks. Tasks write output data to their assigned buffer locations, and other tasks read from these buffers at predetermined times, simplifying data flow management in parallel operations without requiring complex inter-task coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If buffer memories are assigned to clock pulses for deterministic communication, then communication between tasks becomes predictable, but memory resource requirements increase

Engineering Contradiction:
Improvecommunication determinismVSAvoidmemory resource requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Buffer memory regions serve multiple purposes: they act as output buffers for one task and input buffers for another task at different times. This multi-functionality allows the same memory resources to support deterministic communication across multiple task pairs, reducing overall memory requirements while maintaining predictability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Buffer memory contents are discarded and recovered in a cyclical manner according to the time grid. Once data is read from a buffer by the consuming task, the buffer location becomes available for new data from the producing task. This recovery mechanism allows repeated use of the same memory resources, reducing total memory requirements while ensuring deterministic data availability.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS12487632B2Method for operating a data processing system
Publication Date: 2025.12.02 ROBERT BOSCH GMBH
  • US12487632B2 patent drawing
  • US12487632B2 patent drawing
  • US12487632B2 patent drawing

AI summary

A method for operating a data processing system for processing data, which repeatedly executes a plurality of data processing tasks. The method includes the following steps for the operation of the data processing system: executing a synchronization function in each clock pulse before the start of the relevant data processing task to achieve synchronization of the buffer memories for a plurality of data processing units; executing the individual data processing tasks at their relevant repetition rate in the time grid on one of the data processing units of the data processing system; outputting output data by the individual data processing tasks into respectively provided memory areas of the buffer memory assigned to the clock pulse of the grid; and reading in input data by the individual data processing tasks from respectively provided memory areas of the buffer memory which are assigned to the preceding clock pulses of the grid.