Time-Interleaved ADC Calibration Using Unaliased Spectrum Filtering
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Solution Overview
Problem
Time-interleaved Analog-to-Digital Converter (ADC) systems face performance degradation due to gain and phase mismatches between ADC cores, making it impossible to distinguish between input signal components and error signal components when the input signal has components evenly distributed around the sample frequency, leading to convergence issues in adaptive correction algorithms.
Innovation Solution
The implementation of digital filters that selectively filter the unaliased regions of the ADC output spectra before applying adaptive correction techniques, allowing for effective gain and phase mismatch correction by isolating the signal components and removing aliasing artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If adaptive correction algorithms use the entire spectrum of the input signal for gain and phase correction, then correction accuracy is improved, but convergence fails when input signal components are symmetric around Fs/4 due to inability to distinguish signal from error components
Solution Approach 1:
The patent segments the signal spectrum into aliased and unaliased regions, using only the unaliased region for correction algorithm input. This segmentation isolates the useful signal components from the problematic symmetric components that cause convergence failure, allowing the correction algorithm to operate on a purified signal subset.
Solution Approach 2:
The patent extracts and removes the aliased signal components from the spectrum before applying the correction algorithm. By taking out only the unaliased region containing genuine signal information and excluding the symmetric components around Fs/4, the algorithm receives clean input that enables both accurate measurement and reliable convergence.
2Productivity
If time-interleaved ADC systems operate with multiple ADC cores to achieve higher sample rates, then productivity is improved, but gain and phase mismatches between cores degrade signal accuracy
Solution Approach 1:
The patent implements a feedback-based correction system where the correction algorithm continuously estimates gain and phase mismatches from the unaliased signal region and adjusts the ADC core outputs accordingly. This closed-loop feedback mechanism compensates for the mismatches introduced by parallel ADC operation, maintaining signal accuracy while preserving the high sample rate capability.
Solution Approach 2:
The patent changes the parameter set used for correction by restricting the algorithm to operate only on the unaliased frequency region rather than the entire spectrum. This parameter change (selecting a specific frequency subset) allows the system to tolerate the presence of multiple ADC cores with mismatches, as the corrected parameters are derived from a clean signal subset that reveals the true mismatch characteristics.
3Reliability
If digital filters are added to isolate unaliased regions before correction, then convergence reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements digital filters within the existing DSP correction architecture, allowing the same processing unit to perform both filtering and correction functions. This multi-functionality approach adds the necessary spectral isolation capability without proportionally increasing overall system complexity, as the filters share the computational infrastructure already present for correction algorithms.
Data Source
AI summary
A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.