Time-Interleaved ADC Control Using Dynamic Sub-ADC Selection
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (TI-ADCs) face imperfections due to sub-ADC mismatches, leading to output imperfections like spurious tones and signal-dependent distortion, which existing calibration techniques struggle to address efficiently in terms of speed, power consumption, and reliability.
Innovation Solution
Implementing controlling circuitry to manage a pool of sub-ADCs, allowing for randomized selection and dynamic adaptation of operational parameters such as supply voltage and sampling frequency to maintain an optimal set size, ensuring efficient processing capacity utilization and minimizing imperfections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration techniques are used to correct sub-ADC mismatch errors, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and addresses only the dominant mismatch error component (DC offset) through a simplified calibration process that corrects the most significant error source, thereby improving measurement precision without implementing complex multi-parameter calibration systems
Solution Approach 2:
The patent changes the calibration approach by using a single-tone test signal and correcting only the DC offset parameter, rather than attempting to correct all mismatch parameters (gain, timing, offset) simultaneously, thus reducing device complexity while maintaining acceptable precision
2Productivity
If fast calibration is implemented to reduce calibration time, then productivity is improved, but measurement precision and reliability may deteriorate
Solution Approach 1:
The patent extracts and corrects only the dominant DC offset error component during calibration, rather than attempting comprehensive correction of all mismatch parameters, enabling faster calibration while achieving sufficient precision for the application
Solution Approach 2:
The patent applies partial calibration action by correcting only the most significant error source (DC offset) rather than performing complete calibration of all parameters, achieving acceptable precision with reduced calibration time and complexity
3Reliability
If background calibration is performed to avoid operational disturbances, then reliability is improved, but calibration time and power consumption increase
Solution Approach 1:
The patent implements periodic background calibration where the ADC alternates between normal operation and calibration modes, allowing calibration to be performed without interrupting overall system functionality, thus maintaining reliability while limiting calibration time through periodic execution
Solution Approach 2:
The patent makes the calibration process dynamic by allowing it to occur in the background during normal operation rather than requiring a static, dedicated calibration phase, enabling operational continuity while managing calibration time through dynamic resource allocation
4Measurement precision
If redundant sub-ADCs are used to randomize mismatch effects, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent converts the harmful deterministic spurious tones caused by mismatch into beneficial random noise by using a pseudo-random sub-ADC selection sequence, thereby improving measurement precision without requiring redundant sub-ADC hardware through the relationship: deterministic error + randomization = random noise
5Productivity
If sub-ADC conversion speed is increased to handle higher bandwidth, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent segments the high-speed conversion task across multiple slower sub-ADCs operating in parallel with time-interleaved architecture, where each sub-ADC processes a subset of samples, thereby achieving high overall bandwidth while each individual sub-ADC operates at lower power consumption
Solution Approach 2:
The patent makes each sub-ADC multi-functional by enabling it to be dynamically selected for different sample processing tasks through the controller, allowing the same sub-ADC pool to handle varying bandwidth requirements and adjust power consumption accordingly through selective activation
Data Source
AI summary
The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample. Corresponding TI-ADC, wireless communication receiver, wireless communication node, method and computer program product are also disclosed.