Time-Interleaved Electronic Circuit Testing System

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Solution Overview

Problem

The existing methods for testing integrated circuits are time-consuming and require multiple signal channels, limiting the number of chips that can be tested in parallel due to the need for separate channels for each chip, which increases testing time and costs.

Innovation Solution

A system and method for testing electronic circuits that includes a comparator and a comparison result recorder, capable of receiving test signals and ideal response signals, and transmitting test result signals, allowing for parallel testing with reduced signal channels through time-interleaved signal transmission and demultiplexing circuitry, enabling efficient testing of multiple circuits on a semiconductor substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate signal channels are used for each chip under test, then the reliability of signal transmission is improved, but the device complexity and test time increase due to the need for multiple channels

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidsignal channel complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple signal channels into a single shared channel by time-division multiplexing. Test signals and ideal response signals are multiplexed together in time slots, allowing multiple chips to be tested using one physical channel instead of requiring separate channels for each chip, thereby reducing device complexity while maintaining signal transmission reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic channel allocation where a single signal channel is dynamically assigned to different chips at different time slots. The channel is shared among multiple chips through time-division multiplexing, allowing the system to adaptively manage signal transmission resources and reduce the number of physical channels needed

Inventive Principle:
Principle #15Dynamics

2Productivity

If more chips are tested in parallel, then the productivity is improved, but the device complexity increases due to the need for more signal channels

Engineering Contradiction:
Improvetesting throughputVSAvoidsignal channel requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from spatial multiplexing (multiple parallel channels) to temporal multiplexing (time-division sharing). By adding the time dimension to signal transmission, multiple chips can be tested in parallel using a single channel through time-division multiplexing, increasing productivity without proportionally increasing device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent makes a single signal channel universal by allowing it to serve multiple chips sequentially through time-division multiplexing. The same physical channel is reused across different time slots for different chips, enabling one channel to perform the function of multiple channels and thereby increasing testing capacity without proportional increases in hardware complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If test time is reduced by parallel testing, then the productivity is improved, but the loss of time for coordinating multiple channels increases

Engineering Contradiction:
Improvetesting speedVSAvoidchannel coordination time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the channel coordination overhead by eliminating the need for multiple separate channels. By using a single shared channel with time-division multiplexing, the system removes the coordination complexity associated with managing multiple simultaneous channels, reducing the time lost to channel management while maintaining parallel testing capability

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9003254B2Methods and systems for testing electronic circuits
Publication Date: 2015.04.07 MA SSU PIN
  • US9003254B2 patent drawing
  • US9003254B2 patent drawing
  • US9003254B2 patent drawing

AI summary

A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment.