Time-Interleaved Digital-to-Time Converter for Low-Delay Clock Correction
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Solution Overview
Problem
Existing clock signal generation methods for electronic devices often result in long absolute delays and require precise duty cycles, which can be power-intensive and inefficient, especially when using fractional-N dividers and phase-locked loops.
Innovation Solution
An integrated circuit with a digital-to-time converter circuit that uses two capacitors and selectively coupled current sources to generate adjusted clock signals with delays proportional to digital quantization errors, reducing jitter and eliminating the need for duty cycle calibration, allowing for lower oscillator frequencies and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a fractional-N divider and phase-locked loop are used to generate clock signals, then clock signal generation is achieved, but long absolute delay and high power consumption occur
Solution Approach 1:
The patent segments the clock signal generation process into multiple parallel integer divider channels instead of using a single fractional-N divider. Each channel processes a portion of the frequency division independently, reducing the absolute delay through parallel processing while maintaining accuracy through digital filtering and averaging of the divided signals.
Solution Approach 2:
The patent replaces the traditional phase-locked loop mechanism with a digital filtering and averaging approach. Instead of using analog phase detection and voltage-controlled oscillators that consume high power, the invention uses digital logic circuits to achieve frequency synthesis with lower power consumption and reduced delay.
2Ease of operation
If fractional-N divider is used to divide clock frequency, then frequency division is achieved, but precise duty cycle calibration is required
Solution Approach 1:
The patent implements self-correcting digital filtering that automatically compensates for duty cycle variations without external calibration. The digital filter continuously adjusts the averaged divided signal based on feedback from multiple parallel channels, eliminating the need for manual duty cycle calibration while reducing system complexity.
3Use of energy by moving object
If reference clock frequency is reduced to lower power consumption, then power efficiency improves, but clock signal generation becomes problematic
Solution Approach 1:
The patent transitions from temporal frequency domain operations to spatial parallel channel domain operations. By using multiple parallel integer divider channels operating simultaneously, the system achieves frequency synthesis at lower reference clock frequencies while maintaining reliability through spatial diversity and digital signal averaging across multiple channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution shortens input-output absolute delay, eliminates the need for precise duty cycle calibration, and enables lower oscillator frequencies, thereby reducing power consumption and improving clock signal generation efficiency.
Implementation Method 1
A first capacitor is charged with a first current corresponding to a first digital quantization error during a first portion of a first period of the divided clock and a second capacitor is charged during a first portion of a next period of the divided clock signal with a second current corresponding to a second digital quantization error
Data Source
AI summary
A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.