Time-Interleaved Decision Feedback Equalizer Speculation
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Solution Overview
Problem
Digital transmission signals are susceptible to degradation due to Intersymbol Interference (ISI) and noise, which existing automatic adaptive equalizers struggle to address effectively, especially at high frequencies, and require complex calibration mechanisms to avoid race conditions at varying data rates.
Innovation Solution
The implementation of a time-interleaved decision feedback equalizer that employs speculation using auto-aligned multiplexers insensitive to their selection input during a fraction of the clock period, allowing the removal of flip-flops and eliminating the need for data-rate-dependent clock phase calibration, thereby reducing delay and preventing race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If speculation technique is used with multiplexer selection delay lower than summer settling delay, then operation speed is improved, but race conditions occur at varying data rates
Solution Approach 1:
The patent applies preliminary action by performing speculative equalization decisions before the final decision is available. Two sampler circuits generate tentative decisions in advance, and the multiplexer selects between them based on preliminary feedback. This allows the system to operate at higher speeds by preparing decisions ahead of time, while the calibration mechanism ensures reliability across different data rates by adjusting the multiplexer clock phase to prevent race conditions.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the multiplexer clock phase as a function of data rate. The calibration mechanism modifies the phase parameter to optimize the timing relationship between the multiplexer selection and the sampler decisions. This allows the system to maintain reliable operation across varying data rates while benefiting from the speed improvement of the speculation technique.
2Loss of time
If flip-flop is removed from multiplexer output to reduce delay, then critical timing loop delay is reduced, but additional measures are required to avoid race conditions
Solution Approach 1:
The patent applies the extraction principle by removing the flip-flop from the critical timing loop at the multiplexer output. This eliminates the flip-flop propagation delay, reducing the overall timing loop delay and enabling faster operation. The calibration mechanism is introduced as a separate entity to handle the race condition prevention, rather than relying on the flip-flop for timing synchronization.
Solution Approach 2:
The calibration mechanism serves as an intermediary that mediates between the reduced-delay timing loop and the race condition prevention requirement. By adjusting the multiplexer clock phase, the calibration mechanism ensures proper timing alignment without requiring the flip-flop, thus achieving both speed improvement and reliability.
3Reliability
If direct feedback DFE is used to compensate for signal loss, then signal quality is improved, but settling time requirement increases speed constraints
Solution Approach 1:
The patent applies preliminary action by implementing speculative equalization that generates tentative decisions in advance of the final decision. The two sampler circuits produce speculative decisions based on preliminary signal processing, allowing the system to prepare equalization corrections ahead of time. This reduces the settling time requirement while maintaining signal quality compensation through the direct feedback path.
Solution Approach 2:
The patent employs dynamics by using time-interleaved sampling slices that operate in parallel with different timing. The speculative feedback connection dynamically selects between multiple sampler decisions based on the timing requirements, allowing the system to adapt to different data rates and reduce the effective settling time constraint while maintaining signal quality.
Data Source
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AI summary
Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.