Time Interleaved Scan System for Processor Core Testing
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Solution Overview
Problem
Current scan architectures for testing processor cores are unable to fully exploit high-frequency signals from test equipment due to challenges in timing closure and power consumption, leading to increased test costs and reduced efficiency.
Innovation Solution
A serializer/deserializer (SERDES) scheme that partitions high-speed data into multiple parallel phases of lower frequencies, allowing processor cores to be tested efficiently without imposing additional timing closure penalties, and reduces power consumption by staggering clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-frequency signals from test equipment are used for scanning processor cores, then test speed and efficiency are improved, but timing closure challenges and power consumption increase
Solution Approach 1:
The patent divides the high-frequency scanning operation into multiple interleaved lower-frequency channels. Each processor core is assigned to a specific phase with a lower clock frequency, allowing parallel testing across multiple cores while maintaining manageable timing closure and reducing peak power consumption compared to a single high-frequency channel.
2Productivity
If high-frequency signals are used for scanning processor cores, then test efficiency is improved, but timing closure becomes more difficult
Solution Approach 1:
The scanning operation is segmented into multiple phases, each operating at a lower frequency that is easier to timing-close. The deserializer divides the high-speed input into multiple lower-speed parallel streams, allowing each processor core to be tested independently at manageable clock rates while maintaining overall high test efficiency through parallel operation.
3Ease of manufacture
If traditional scan architecture is used, then implementation is simpler, but test cost is higher
Solution Approach 1:
The patent introduces a SERDES (serializer/deserializer) module as an intermediary between the test equipment and the processor cores. This intermediary converts the single high-speed test signal into multiple parallel lower-speed signals that can be distributed to multiple cores, enabling cost-effective parallel testing while maintaining compatibility with standard test equipment.
4Reliability
If multiple processor cores are tested in parallel, then test coverage is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by assigning different processor cores to different phases with staggered clock cycles. Cores are tested in an interleaved manner where not all cores are active simultaneously at full power, reducing peak power consumption while maintaining comprehensive test coverage across all cores through systematic rotation through the phases.
Data Source
AI summary
Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.