Hybrid Time Interleaver Architecture for Deep Interleaving With Less Memory
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Solution Overview
Problem
Current time interleavers and deinterleavers in digital communication systems, particularly in BICM systems using QC LDPC and QAM, face inefficiencies in implementation and resource usage, especially in reducing memory requirements for portable devices, and existing specifications like DVB-NGH lack detailed methods for generating time-interleaved transmission sequences.
Innovation Solution
A hybrid time interleaver and deinterleaver design combining block interleaving and convolutional interleaving, with a row-column block interleaver and convolutional interleaver configuration, that reduces memory usage by employing efficient addressing schemes and logical data rearrangement, allowing for a more compact and cost-effective implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional time interleavers and deinterleavers are implemented in digital communication systems, then time interleaving function is achieved, but memory requirements increase and device size increases
Solution Approach 1:
The time interleaver is divided into multiple functional blocks: a block interleaver that performs initial interleaving, and a convolutional interleaver that performs additional interleaving. This segmentation allows each block to use minimal memory while collectively achieving the required time interleaving depth, thus reducing total memory requirements compared to a single large interleaver.
Solution Approach 2:
The patent transitions from conventional single-dimension time interleaving to a two-dimensional approach by combining block interleaving (spatial arrangement) with convolutional interleaving (temporal arrangement). This dimensional change enables the system to achieve equivalent time diversity with reduced memory by utilizing both spatial and temporal dimensions for data distribution.
2Reliability
If conventional time interleavers and deinterleavers are implemented in digital communication systems, then time interleaving function is achieved, but device complexity and cost increase
Solution Approach 1:
The complex time interleaving function is segmented into two simpler, well-understood components: block interleaving and convolutional interleaving. Each component uses established, simple algorithms that are easier to implement than a single complex interleaver, reducing overall device complexity while maintaining the required time interleaving performance.
Solution Approach 2:
The patent merges two conventional interleaving techniques (block and convolutional) into a unified time interleaving system. This combination leverages the simplicity and efficiency of each individual technique, resulting in a system that is easier to implement than conventional approaches while achieving superior time interleaving depth and performance.
3Reliability
If hybrid interleaving combining block interleaving and convolutional interleaving is used, then time interleaving depth increases, but device size increases
Solution Approach 1:
The time interleaving depth is achieved through segmentation of the interleaving function across multiple blocks rather than requiring a single large memory structure. The block interleaver handles initial distribution while the convolutional interleaver extends the time diversity, allowing deep interleaving without proportionally increasing device area.
Solution Approach 2:
The patent achieves increased time interleaving depth by utilizing multiple dimensions of data arrangement (block structure and convolutional structure) rather than relying solely on increased memory depth. This dimensional approach allows deep interleaving to be achieved with compact device architecture by exploiting temporal and spatial arrangements simultaneously.
Data Source
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AI summary
A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.