Time-Interleaving Circuit With XOR Glitch Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time interleaving circuits experience glitches in output data due to misalignment of clock signals, leading to brief state transitions that are not synchronized with the clock signal duration.
Innovation Solution
The circuit employs two loading stages with complementary clock signals, each serializing data and using exclusive disjunction logic to buffer or invert data, eliminating the need for a clock signal at the output stage, which serializes data based on phased state changes of the loading stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are used to serialize data in loading stages, then data serialization is achieved, but misalignment in clock signal timing introduces glitches in output data
Solution Approach 1:
An output stage is introduced as an intermediary between the loading stages and the final output. This output stage uses exclusive disjunction logic to combine data from multiple loading stages, ensuring that glitches from individual stages are neutralized. The intermediary stage acts as a buffer that synchronizes and stabilizes the combined output without requiring additional clock signals.
Solution Approach 2:
The patent removes the clock signal and selection signal from the output stage, extracting the problematic timing control elements that cause glitches. By eliminating these signals, the system avoids the timing misalignment issues that would otherwise propagate to the final output, while still achieving data serialization through the phased operation of loading stages.
2Ease of operation
If a selection signal is used at the output stage to serialize data, then data selection between loading stages is achieved, but timing misalignment between clock signals causes glitches
Solution Approach 1:
The selection signal is completely removed from the output stage. Instead of using a traditional multiplexer with selection signals, the patent uses exclusive disjunction logic that automatically selects and combines data from loading stages based on their phased operation. This extraction of the selection signal eliminates the source of timing misalignment and glitch generation.
Solution Approach 2:
The loading stages self-select their output contribution through their inherent phased timing. Each loading stage operates on a different phase of the clock signal, automatically determining when its data should be output without requiring external selection signals. The exclusive disjunction logic at the output stage simply combines these self-timed outputs, eliminating the need for complex selection control.
Data Source
AI summary
Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.