Time Measuring Circuit Dynamic Clock Switching for Counter Bit Efficiency
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Solution Overview
Problem
Existing time measuring circuits face insufficiency in counter bits when measuring large changes in target time, particularly in temperature-dependent delay time measurements, due to high-frequency clock signal usage.
Innovation Solution
A time measuring circuit with an oscillating circuit generating low-speed and high-speed clock signals, switching from low-speed to high-speed when elapsed time reaches a set value calculated by subtracting a predetermined value from a preliminary measurement, ensuring stable time measurement even with large target time changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency clock signal is used to improve time resolution, then time resolution is improved, but the counter bit number increases requiring greater circuitry resources
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable during measurement. The system starts with a low-frequency clock signal to save counter bits, then dynamically switches to a high-frequency clock signal when the remaining time to be measured becomes small. This dynamic frequency adjustment allows the system to achieve high time resolution only when necessary, rather than maintaining high frequency throughout the entire measurement period, thus reducing the required counter bit number while still achieving accurate measurements.
2Device complexity
If a low-speed clock signal is used to reduce counter bit number, then circuitry resources are suppressed, but time resolution deteriorates
Solution Approach 1:
The system dynamically adjusts the clock signal frequency based on the measurement progress. It begins with a low-frequency clock signal that requires fewer counter bits and reduces circuitry resources. As the measurement approaches completion (when the remaining time becomes small), the system switches to a high-frequency clock signal to achieve high time resolution for the final measurement phase. This dynamic approach ensures adequate time resolution is achieved when needed while minimizing resource requirements during the measurement process.
3Ease of operation
If the switch from low-speed to high-speed clock signal is based on a fixed predetermined value, then the switching timing is simple to control, but insufficiency in counter bits occurs when target time changes significantly
Solution Approach 1:
The patent implements feedback by using the preliminary measurement result to dynamically determine the switching timing. The system first performs a preliminary measurement using the low-frequency clock signal to obtain a preliminary value. Then, it calculates the switching timing by subtracting a predetermined value from this preliminary value. This feedback mechanism ensures that the switching timing adapts to the actual measurement conditions, preventing counter bit insufficiency even when the target time changes significantly, while maintaining relatively simple control logic.
Data Source
AI summary
A time measuring circuit is provided with an oscillating circuit configured to generate a low-speed clock signal and a high-speed clock signal; and a measuring circuit configured to measure target time based on clock number of the low-speed clock signal and the high-speed clock signal outputted from the oscillating circuit, wherein the low-speed clock signal has a relatively low frequency and the high-speed clock signal has a relatively high frequency. The oscillating circuit is configured to switch from outputting the low-speed clock signal to outputting the high-speed clock signal when elapsed time from when a measurement of the target time started reaches a set value, and the set value is calculated by subtracting a predetermined value from a preliminary value which is provided by a preliminary measurement measuring the target time using only the low-speed clock signal.