Time-Multiplexed BRAM for Multiple FIFOs
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Solution Overview
Problem
Current FPGA implementations face inefficiencies when using block random access memory (BRAM) for first-in-first-out (FIFO) memories, as they require smaller memory blocks and more flexible port configurations than provided by standard BRAMs, leading to resource wastage.
Innovation Solution
The implementation of time-multiplexed memory in integrated circuits, where a BRAM circuit with multiple ports is used, with FIFO logic and multiplexer logic to selectively couple output interfaces to the ports, allowing for the creation of multiple FIFOs using a shared memory space, with each BRAM clock signal having at least twice the frequency of the FIFO clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a BRAM is used for each FIFO memory, then each FIFO gets dedicated memory resources, but the overall resource utilization efficiency decreases
Solution Approach 1:
Multiple FIFO memories are merged onto a single BRAM block by time-multiplexing the read and write ports. The BRAM shares its memory array among multiple FIFOs, with each FIFO accessing the shared memory at different time slots, thereby consolidating multiple dedicated memory blocks into one shared resource and improving overall utilization efficiency.
Solution Approach 2:
The BRAM block is designed to serve multiple functions simultaneously - it acts as shared memory for multiple FIFOs. The single BRAM structure provides universal access to multiple FIFO memories through time-multiplexed port control, allowing one memory block to perform the work of multiple dedicated blocks.
2Quantity of substance
If standard BRAMs are used, then memory blocks are provided, but flexibility for different port configurations and sizes is limited
Solution Approach 1:
The port configuration of the BRAM is made dynamic through time-multiplexing. Instead of having fixed dedicated ports for each FIFO, the read and write ports are dynamically reassigned to different FIFOs at different time slots. This dynamic reconfiguration allows the same physical ports to serve different functional purposes, providing flexibility for various port configurations and FIFO sizes.
Data Source
AI summary
Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.