Time-Multiplexed Hardware Acceleration in Programmable ICs

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Solution Overview

Problem

Current programmable integrated circuits (ICs) face inefficiencies in implementing hardware-accelerated functions due to limitations in partial reconfiguration, where data independence is not fully leveraged to optimize concurrent processing across multiple reconfiguration regions.

Innovation Solution

A method is introduced that associates each function with an accelerator binary image and determines data independence to schedule these images for concurrent implementation across partial reconfiguration regions in a programmable IC, utilizing a hardware scheduler to time-multiplex hardware acceleration and implement data-independent groups of accelerator binary images concurrently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If partial reconfiguration is used to dynamically reconfigure regions of programmable circuitry, then the ability to change circuitry in specific regions is improved, but the inability to change PR region boundaries and the fixed connectivity constraints reduce flexibility and adaptability

Engineering Contradiction:

Improvecircuitry reconfiguration capabilityVSAvoidPR region boundary constraints

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the programmable IC into multiple independent partial reconfiguration regions (PR regions), each capable of being reconfigured independently. This allows different functions to be implemented in different regions simultaneously, improving adaptability while maintaining manageable complexity through modular segmentation rather than monolithic reconfiguration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a time-multiplexing dimension to the reconfiguration process, allowing PR regions to be reconfigured at different times without interrupting overall system operation. This temporal dimension adds flexibility beyond spatial reconfiguration constraints, enabling dynamic adaptation while maintaining system stability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If hardware acceleration is implemented using accelerator binary images, then processing speed for specific functions is improved, but the inability to leverage data independence for concurrent processing increases compute time

Engineering Contradiction:

Improvehardware acceleration speedVSAvoidcompute time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent performs preliminary analysis of the program code to identify data independence relationships between functions before hardware acceleration is applied. This preliminary classification enables the scheduler to optimize the execution order and concurrency of accelerator binary images, leveraging data independence to reduce compute time while maintaining high processing speeds.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a dynamic scheduling mechanism that adapts the execution sequence of accelerator binary images based on data independence analysis. The scheduler dynamically adjusts which PR regions are reconfigured when and in what order, optimizing compute time by executing data-independent functions concurrently while maintaining hardware acceleration speeds.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If multiple accelerator binary images are loaded into partial reconfiguration regions, then hardware acceleration coverage is improved, but the inability to concurrently execute data-independent functions increases total processing time

Engineering Contradiction:

Improvehardware acceleration coverageVSAvoidconcurrent processing capability

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the workload into multiple accelerator binary images that can be independently loaded into different PR regions. By analyzing data independence relationships, the system identifies which segments can execute concurrently, improving productivity while maintaining comprehensive hardware acceleration coverage through multi-region deployment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements periodic scheduling of accelerator binary image loading and execution based on data independence analysis. The scheduler periodically reconfigures different PR regions with different accelerator images in an optimized sequence, enabling concurrent execution of data-independent functions while maintaining broad hardware acceleration coverage.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS11449347B1Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit

Publication Date: 2022.09.20 XILINX INC

AI summary

Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.