Time-Multiplexed LFSR CRC Generation for Lower Area and Power
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Solution Overview
Problem
As computing environments evolve, the increasing complexity and size of linear feedback shift registers (LFSR) required for cyclic redundancy check (CRC) calculations consume more space and power, especially with higher bits per data word, leading to inefficiencies in data transfer reliability.
Innovation Solution
A method for generating CRC values using smaller and fewer LFSR circuits by separating CRC calculations into sub-calculations and employing programmable XOR engines with table lookups, allowing for shared LFSR circuits between link CRC and end-to-end CRC calculations, and time-multiplexing across multiple links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LFSR circuits are designed to handle more bits per data word, then data transmission capability is improved, but hardware surface area increases significantly
Solution Approach 1:
The patent divides the LFSR circuit into multiple smaller LFSR instances, each handling a portion of the data word. For example, a 64-bit data word is processed by multiple smaller LFSRs working in parallel or sequentially, rather than one large LFSR. This segmentation reduces the surface area of each individual LFSR while maintaining the overall data transmission capability.
Solution Approach 2:
The patent introduces time multiplexing as an additional dimension, allowing a single LFSR circuit to service multiple links sequentially over time. The LFSR is shared across multiple PCIe links by switching its input/output connections based on which link currently needs CRC calculation, effectively reducing the number of physical LFSR circuits needed.
2Reliability
If multiple LFSR circuits are implemented for multiple CRC values, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple LFSR circuits into a single shared LFSR that services multiple PCIe links through time multiplexing. Instead of having separate LFSR instances for each link (which would consume more power), one LFSR is time-shared across multiple links, reducing overall power consumption while still providing CRC calculation capability for all links.
Solution Approach 2:
The single LFSR circuit is designed to be universal, capable of calculating CRC values for multiple different PCIe links and multiple different data widths. By configuring the LFSR to handle different input sizes and serving multiple links, it replaces what would traditionally require multiple dedicated LFSR circuits, thereby reducing power consumption.
3Measurement precision
If LFSR circuit size increases with more bits per data word, then CRC calculation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the CRC calculation task across multiple smaller LFSR circuits rather than using one large complex LFSR. Each smaller LFSR handles a specific portion or specific link, making individual circuits simpler while collectively achieving the required CRC accuracy for the full data width through coordinated operation.
Data Source
AI summary
Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.