Time Multiplexed Memory Bus for Mixed Interface Access
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Solution Overview
Problem
Memory controllers in data processing systems with multiple types of memory require separate dedicated interfaces, leading to increased cost and size due to the need for numerous I/O pins to manage different input/output transfer rates and characteristics.
Innovation Solution
Implementing a time division multiplexed signal bus that allows different types of memory to be accessed at different rates using a shared bus, reducing the number of I/O pins required and enabling efficient bandwidth allocation by using device select signals and clock signals at varying rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate dedicated interfaces are used for each memory type, then memory access performance and reliability are improved, but device complexity and cost increase due to more I/O pins
Solution Approach 1:
The patent merges multiple dedicated memory interfaces into a single shared bus that can accommodate different memory types (SRAM, DRAM, Flash) through time-division multiplexing. The memory controller shares I/O pins and bus resources among different memory devices by assigning different time slots, eliminating the need for separate dedicated interfaces for each memory type while maintaining reliable access to each memory type through controlled timing and selection signals.
Solution Approach 2:
The shared bus is designed with universal functionality to support multiple memory types through a single interface. The memory controller uses device select signals and timing control to enable the same physical bus to communicate with different memory devices (SRAM, DRAM, Flash) having different access characteristics, making the interface multi-functional rather than dedicated to a single memory type.
2Adaptability or versatility
If separate dedicated interfaces are used for each memory type, then memory access characteristics are optimized, but manufacturing cost increases due to more components
Solution Approach 1:
The patent combines multiple dedicated interfaces into a single shared bus structure, reducing the total number of components and I/O pins required. By implementing time-division multiplexing, the system maintains optimized access characteristics for different memory types while using fewer physical resources, thereby reducing manufacturing cost and simplifying production.
Solution Approach 2:
The memory controller adjusts timing parameters, clock rates, and control signals dynamically based on which memory type is being accessed. By changing these operational parameters rather than using separate hardwired interfaces for each memory type, the system achieves memory-specific optimization without the cost of dedicated hardware paths for each memory type.
3Device complexity
If time division multiplexing is implemented, then device complexity is reduced, but bandwidth allocation and data transfer efficiency become more challenging
Solution Approach 1:
The system implements periodic time-division multiplexing where different memory devices are accessed in sequential time slots on the shared bus. The memory controller uses periodic selection signals to switch between SRAM, DRAM, and Flash devices, ensuring that each memory type receives regular periodic access opportunities while maintaining simple hardware architecture through this rhythmic time-slot allocation.
Solution Approach 2:
The memory controller dynamically adjusts the time slot allocation and access timing based on system needs. By making the multiplexing schedule flexible rather than fixed, the system can optimize bandwidth distribution to different memory types according to current operational requirements, improving productivity while maintaining reduced device complexity.
Data Source
AI summary
A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.