Time-Multiplexed Sampling Circuit for Low-Power High-Bandwidth ADCs
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Solution Overview
Problem
High-frequency signal sampling circuits face challenges in reducing power consumption while maintaining bandwidth and linearity, as reducing buffer circuit bandwidth leads to phase shift and attenuation due to charge redistribution, and increasing it increases power consumption and input capacitance.
Innovation Solution
A sampling circuit with multiple channels operating in time-multiplexed fashion, using output switches to reduce power consumption by disconnecting track-and-hold circuits from ADC inputs during tracking, and employing a control circuit to manage sampling and holding modes, allowing reduced drive capability and minimizing charge redistribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the bandwidth of the buffer circuit is reduced to save power, then power consumption decreases, but phase shift and attenuation occur due to charge redistribution
Solution Approach 1:
The sampling circuit is divided into multiple parallel sampling channels (first sampling channel, second sampling channel, etc.) that operate in time-multiplexed fashion. Each channel has its own track-and-hold circuit and buffer circuit, allowing the system to distribute the signal loading across multiple channels rather than relying on a single high-power buffer, thus reducing overall power consumption while maintaining signal accuracy.
Solution Approach 2:
The output switch dynamically connects or disconnects the track-and-hold circuit from the ADC input based on the operational mode. During tracking mode, the output switch disconnects the buffer from the ADC input, allowing the buffer to operate with minimal load and reduced power consumption. During holding mode, the switch connects the buffered signal to the ADC input for conversion.
2Reliability
If the bandwidth of the buffer circuit is increased to maintain signal accuracy, then phase shift and attenuation are reduced, but power consumption increases
Solution Approach 1:
By segmenting the sampling function across multiple parallel channels, each channel can use a lower-power buffer circuit. The collective bandwidth of all channels achieves the required signal accuracy, while individual buffer power consumption is reduced. This segmentation allows the system to meet bandwidth requirements without requiring each buffer to operate at high power continuously.
Solution Approach 2:
The buffer circuits operate periodically in time-multiplexed fashion with the sampling channels. During tracking mode, buffers operate with minimal load; during holding mode, they transfer signals to ADC inputs. This periodic operation allows buffers to maintain signal accuracy during critical periods while consuming reduced power during other periods.
3Speed
If the size of the buffer circuit is scaled up to improve bandwidth, then bandwidth increases, but input capacitance increases limiting the sampling transistor bandwidth
Solution Approach 1:
The sampling function is segmented across multiple parallel channels, each with its own buffer circuit. This segmentation allows the sampling transistor to drive multiple smaller buffer circuits simultaneously rather than one large buffer, effectively increasing the total bandwidth capability while keeping individual buffer input capacitances low enough to maintain high sampling rates.
Solution Approach 2:
The output switch dynamically controls the connection between the track-and-hold circuit and ADC input. During tracking mode, the switch disconnects the buffer from the ADC input, minimizing the effective load capacitance seen by the sampling transistor. This dynamic switching allows the sampling transistor to operate at high bandwidth without being limited by the total capacitance of all buffers simultaneously.
Data Source
AI summary
A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.