Time Multiplexing Mechanism for Semiconductor Memory Size Efficiency
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Solution Overview
Problem
Memory devices face challenges in efficiently managing data bus traffic and reducing physical size while maintaining data capacity and speed, particularly in accommodating various IO configurations which complicate data management and increase the number of circuits and data lines.
Innovation Solution
Implementing a shared bus system that communicates multiple bits over a reduced number of information lines, leveraging propagation delays to time data transmission and using a multiplexer-control circuit to manage traffic, allowing both read and write operations to utilize the same data lines, thereby reducing the number of data lines required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate data lines are used for read and write operations, then data speed is improved, but the number of data lines increases
Solution Approach 1:
The patent combines separate read and write data lines into a single bidirectional data line that can carry both read and write operations. The data I/O circuitry is configured to selectively couple the data line to either read or write operations based on control signals, eliminating the need for dedicated separate lines for each operation type while maintaining data speed requirements.
Solution Approach 2:
The patent implements dynamic switching of the data line function between read and write modes using control logic. The data I/O circuitry can dynamically reconfigure the data line coupling based on operation type, allowing the same physical infrastructure to adapt to different functional requirements without sacrificing performance.
2Adaptability or versatility
If multiple sets of data I/Os are used to accommodate various IO configurations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal data I/O circuit design where a single data I/O interface can be configured to support multiple IO configurations (X4, X8, X16, X32) through programmable control logic. The data I/O circuitry responds to training sequences and configuration signals to adapt its behavior, eliminating the need for separate dedicated circuitry for each configuration type.
Solution Approach 2:
The patent changes operational parameters of the data I/O circuitry based on detected IO configuration. By monitoring training sequences and configuration signals, the circuit dynamically adjusts its operational characteristics (such as data width, timing, and coupling behavior) to match the required configuration, providing versatility without requiring multiple fixed designs.
3Area of stationary object
If the number of data lines is reduced, then physical size is decreased, but data capacity may be compromised
Solution Approach 1:
The patent employs time-division multiplexing where the reduced number of data lines are activated in periodic sequences to handle different data operations. By carefully timing the activation of data lines for different operations (read, write, different data widths), the system maintains effective data capacity equivalent to having more permanent lines while using fewer physical connections.
Solution Approach 2:
The patent adds the time dimension to data transmission by using bidirectional communication protocols and time-multiplexed data lines. Instead of requiring separate spatial lines for each function, the system uses a single line that switches functions over time, effectively increasing capacity through temporal rather than spatial multiplication.
Data Source
AI summary
A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.