Time Offset Device for Daisy Chain Test Signal Impedance Delay

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Solution Overview

Problem

The accuracy of device testing is compromised due to time delays caused by impedance matching on the transmission path, which are not adequately addressed by existing time offset methods, leading to inconsistent and inaccurate test results across multiple test locations on a daisy chain test platform.

Innovation Solution

A time offset method and device that acquires and analyzes time parameters at each test location to determine offset parameters, allowing for precise adjustment of test clock signals to compensate for impedance-related delays, ensuring all devices receive test signals accurately and consistently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple devices are disposed on a daisy chain test platform for batch inspection, then testing efficiency is improved, but test accuracy deteriorates due to transmission time delays caused by impedance matching variations on different transmission paths

Engineering Contradiction:
Improvetesting efficiencyVSAvoidtest accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies local quality by determining specific offset parameters for each test location on the daisy chain test platform. Each location receives a customized time offset value based on its specific impedance characteristics and transmission path, rather than applying a uniform offset. This localized approach compensates for the varying impedance matching conditions at different positions, thereby maintaining test accuracy across all devices while preserving batch inspection efficiency

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the time offset parameter dynamically based on the test location. By measuring or calculating the impedance characteristics of each transmission path and determining corresponding offset parameters, the system adjusts the test signal timing to compensate for transmission delays. This parameter adaptation resolves the contradiction by ensuring accurate timing compensation for each location while maintaining the batch testing capability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11860226B2Time offset method and device for test signal
Publication Date: 2024.01.02 CHANGXIN MEMORY TECH INC
  • US11860226B2 patent drawing
  • US11860226B2 patent drawing
  • US11860226B2 patent drawing

AI summary

Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.