Time Segmentation Sampling for Channelizer Networks

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Solution Overview

Problem

Typical networking systems face inefficiencies due to high data processing rates exceeding network capacity, leading to complex interconnects and routing tables, especially when using field programmable gate arrays (FPGAs), which require additional pins and internal logic for data exchange between routers.

Innovation Solution

Implementing time segmentation data sampling, where all data for a specific time segment is transmitted over each interface, eliminating the need for inter-router data exchange and simplifying routing tables, thereby reducing interconnects and increasing supported interfaces and system bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If data channels are dedicated to certain interfaces, then routing is simplified, but interconnect complexity increases as routers must interchange data with each other

Engineering Contradiction:
Improverouting simplicityVSAvoidinterconnect complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The data stream is segmented into time samples, with each time sample being transmitted over all interfaces. This segmentation in time domain eliminates the need for spatial segmentation (dedicating channels to interfaces), thereby removing interconnect complexity while maintaining routing simplicity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses periodic transmission of time samples over interfaces. Each interface transmits complete time samples periodically, creating a rhythmic pattern that simplifies routing decisions while eliminating the need for complex inter-router data interchange

Inventive Principle:
Principle #19Periodic action

2Adaptability or versatility

If FPGAs are used for routing, then flexibility is improved, but the number of pins and internal logic required increases

Engineering Contradiction:
Improverouting flexibilityVSAvoidnumber of pins
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent extracts the data interchange function from the FPGA routers themselves. By having each interface independently transmit complete time samples, the need for FPGAs to exchange data with each other is removed, thereby reducing the number of pins and internal logic required while maintaining routing flexibility

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If data processing speed is increased, then productivity is improved, but network capacity becomes insufficient

Engineering Contradiction:
Improvedata processing speedVSAvoidnetwork capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent transitions from spatial distribution of data (different channels on different interfaces) to temporal distribution (all data on all interfaces at different times). This dimensional change allows high-speed processing to proceed without overloading network capacity, as each interface handles complete time samples sequentially rather than sharing bandwidth across multiple channels simultaneously

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7590090B1Time segmentation sampling for high-efficiency channelizer networks
Publication Date: 2009.09.15 LOCKHEED MARTIN CORP
  • US7590090B1 patent drawing
  • US7590090B1 patent drawing
  • US7590090B1 patent drawing

AI summary

A system comprises a processor configured to receive incoming data and configured to apply a subchannelizer algorithm to the received data. The subchannelizer algorithm segments the received data into time segmented data samples and distributes the time segmented data samples into a plurality of data streams for transmission across one of a plurality of interfaces to a network. The system further comprises a register generally coupled to the processor for storing each time segmented data sample prior to transmitting the time segmented data sample across the plurality of interfaces, wherein the time segmented data samples are written to the register at a first frequency and the time segmented data samples are read out of the register at a second frequency. The system is further arranged to receive a plurality of outgoing data streams from the network, and recombine the plurality of outgoing data streams for output to a downlink device.